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Oscillator Configuration and Reset Mechanisms

The document outlines the configuration settings for oscillator operations, including various reset operations such as Power-on Reset (POR) and Brown-out Reset (BOR). It details the functionality of timers like the Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) that ensure proper initialization and stabilization of the oscillator. Additionally, it mentions the Phase Lock Loop (PLL) lock time-out and the importance of configuration registers CONFIG1H and CONFIG2L in managing these settings.

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3 views18 pages

Oscillator Configuration and Reset Mechanisms

The document outlines the configuration settings for oscillator operations, including various reset operations such as Power-on Reset (POR) and Brown-out Reset (BOR). It details the functionality of timers like the Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) that ensure proper initialization and stabilization of the oscillator. Additionally, it mentions the Phase Lock Loop (PLL) lock time-out and the importance of configuration registers CONFIG1H and CONFIG2L in managing these settings.

Uploaded by

Syce
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Oscillator configuration

CONFIG1H: CONFIGURATION REGISTER 1 HIGH


(Phase Lock Loop)
Crystal/ Ceramic resonator operation LP, XT, HS
RC Oscillator mode
CONFIG2L: CONFIGURATION REGISTER 2 LOW
Reset operations
• Power-on Reset (POR)
• MCLR Reset during normal operation (Master CLeaR)
• MCLR Reset during Sleep
• Watchdog Timer (WDT) Reset during normal operation
• Programmable Brown-out Reset (PBOR)
• RESET Instruction
• Stack Full Reset
• Stack Underflow Reset
Power – on Reset (POR)
• VDD pin has high.
• An external RC component is used to create a POR delay.
_____
MCLR
• External power on reset circuit
• There is a noise filter in the reset path, that detects and ignores small
pulses.
• MCLR can be connected to VDD to avoid the RC component
Power- up Timer (PWRT)
• It operates on an internal RC oscillator.
• The chip is in Reset as long as the PWRT is active.
• CONFIG2L register has the corresponding bit
• The PWRT’s time delay allows VDD to rise to an acceptable level.
Oscillator Start-up Timer(OST)
• It provides a 1024 oscillator cycle delay after the PWRT delay is over.
• This additional delay ensures that the crystal oscillator or resonator
has started and stabilized.
• It is invoked only for XT, LP, HS and HS4 modes.
• It is used in POR and wake-up from sleep
PLL lock time-out
• A portion of the power-up timer is used to provide a fixed time-out
• It is sufficient for the PLL to lock to the main oscillator frequency.
• PLL lock time-out is typically 2 ms
• It follows the oscillator start-up time-out(OST)
Brown-out Reset (BOR)
• BOREN – BOR Enable configuration bit in CONFIG2L
• It can disable or enable BOR circuitry.

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