Department of ECE

ACADEMIC YEAR 2023 – 2024

REGULATION 2017

COURSE MATERIAL

EC3352 – DIGITAL SYSTEM DESIGN

1
 Scope
• The purpose of this course is that we:
– Learn what’s under the hood of an electronic
component
– Learn the principles of digital design
– Learn to systematically debug increasingly
complex designs
– Design and build a digital system

2
 Moore’s Law

“If the automobile had followed the same development cycle as the
computer, a Rolls-Royce would today cost $100, get one million
miles to the gallon, and explode once a year . . .”
– Robert Cringley
3
 Scope
• Hiding details when
they aren’t important Application
Software
programs

Operating
device drivers
Systems

instructions

focus of this course

Architecture
registers

Micro- datapaths
architecture controllers

adders
Logic
memories

Digital AND gates

Circuits NOT gates

Analog amplifiers
Circuits filters

transistors
Devices
diodes

Physics electrons

4
We will cover four major things in this
course:

- Combinational Logic (Ch 2)

- Sequential Networks (Ch 3)
- Standard Modules (Ch 5)
- System Design (Chs 4, 6-8)

5
 Overall Picture of CS140
Input

Memory File
Conditions
Pointer
Mux Control
Subsystem

ALU
Control
Memory
Register

Conditions CLK: Synchronizing Clock

6
 Combinational Logic vs Sequential Network
x1 x1
. .
. fi(x) . si fi(x)
. .
xn xn
CLK

Combinational logic: Sequential Networks

yi = fi(x1,..,xn) 1) Memory 2) Time Steps (Clock)
yit = fi (x1t,…,xnt, s1t, …,smt)
Sit+1 = gi(x1t,…,xnt, s1t,…,smt)

7
 Scope
Subjects Building Blocks Theory
Combinational AND, OR, Boolean
Logic NOT,XOR Algebra
Sequential AND, OR, Finite State
Network NOT, FF Machine
Standard Operators, Arithmetics,
Modules Interconnects, Universal Logic
Memory
System Design Data Paths, Methodologies
Control Paths
8
 Part I. Combinational Logic

a ab
ab + cd
b
c e (ab+cd)
d cd
e

• I) Specification
• II) Implementation
• III) Different Types of Gates

9
 Objectives and Outcomes
On completion of this course, students will have
confidence in their abilities to conceive and carry out a
complex digital systems design project in a team of two
or three people. More broadly, they will be ready to
handle substantial, challenging design problems. In
particular, students will be able to:

1. explain the elements of digital system abstractions

such as digital logic,Boolean algebra, flip-flops and
finite-state machines (FSMs).
2, design simple digital systems based on these digital
abstractions, and the "digital paradigm" including
discrete, sampled information.
3. use basic digital tools and devices such as digital
oscilloscopes, PALs, PROMs, and VHDL.
4. work in a design team that can propose, design,
successfully implement, and report on a digital circuit
design project.
5. communicate the purpose and results of a design
project in written and oral presentations.
Where is this course in the CSIE
course map?
(1) Circuits and Micro-Electronics (optional)

THEN
(2) Digital System Design and Laboratory
THEN
(3) Computer Architecture, or
(4) VLSI design, or (5) Embedded System
Design
 Digital vs. Analog Systems
• Difference
• How to bridge these two systems?
AD and DA converter
Expected capabilities for students
(see the demos!)
(1)Understand the Digital System Design
principles
(2) Can write a program for Reverse Engineering
(Read a circuit from the System Design, and
explain its function, by a program)
(3) Can write a program for Forward Design
(Read a finite automata or finite state machine,
then generate the circuits with logic gates)
Hardware Description Languages
1. VHDL (demo)
2. Verilog (demo)
State machines: Moore machine
State machines: Moore machine
State machines: Mealy machine
 VHDL
• VHDL was originally developed at the
request of the U.S Department of Defense
in order to document the behavior of the
ASICs that supplier companies were
including in equipment.
 VHDL
• The idea of being able to simulate the ASICs
from the information in this documentation
was so obviously attractive that
logic simulators were developed that could
read the VHDL files. The next step was the
development of logic synthesis tools that read
the VHDL, and output a definition of the
physical implementation of the circuit.
 logic synthesis
In electronics, logic synthesis is a process by
which an abstract form of desired circuit behavior,
is turned into a design implementation in terms of
logic gates. Common examples of this process
include synthesis of HDLs, including VHDL and
Verilog. Some tools can generate bitstreams for
programmable logic devices such
as PALs or FPGAs, while others target the
creation of ASICs. Logic synthesis is one aspect
of electronic design automation.
 Combinational logic vs.
Sequential logic (with registers)
• A synchronous circuit consists of two kinds of
elements: registers and combinational logic.
Registers (usually implemented as D flip-flops)
synchronize the circuit's operation to the edges
of the clock signal, and are the only elements in
the circuit that have memory properties.
Combinational logic performs all the logical
functions in the circuit and it typically consists
of logic gates.
 Combinational logic and
Sequential logic (example)
 Reverse Engineering
Can write a program for Reverse Engineering
(Read a circuit from the System Design, and
explain its function, by a program)
Results (a finite state machine!)
Mealy machine vs Moore machine
• In the theory of computation, a Moore
machine is a finite-state machine whose
output values are determined solely by its
current state.
• In the theory of computation, a Mealy
machine is a finite-state machine whose
output values are determined both by its
current state and the current inputs.
Can write a program for Forward Design
(Read a finite automata or finite state machine,
then generate the circuits with logic gates)
Example: design a counter that can count from 1
to 5 (and input bits can overlap).
Results (a logic circuit design)
 Two types of results of circuit Implementation
• (1) 電路板 ( 麵包板 , breadboard) or FPGA (field-
programmable gate array)
 Results of Implementation (II)
( 可送台積電 , 聯電製造 )

(2) A chip (ASIC, application specific

integrated circuits)
 That’s why you need the logic
lab in Dept. of CSIE!
To do the FPGA implementation with
breadboard, or chip deign

By writing programs (VHDL, Verilog etc.)!

(and you need debugging, also in hardware, to
be sure that your product is correct!)
THEN you need: logic analyzer ( 邏輯分析儀 ,
4GHz one, for example),
 logic analyzer
• a laboratory test instrument designed to
display and evaluate digital signals. The
device works in a manner similar to the way
that an oscilloscope displays and facilitates the
analysis of analog signals.
• A logic analyzer allows engineers to design,
optimize, and debug the hardware in digital
systems, and can help technicians find and fix
problems in malfunctioning systems.
What is the cost of a product from
design to implementation?
(for a machine/a circuit)

• In terms of total time and money used

 Design goals: constraints=
Design fees + manufacture+ support
 Total Cost of Circuit/Chip
Design
• Cd: design cost, shared by all products N
• Cm: manufacture cost
• Cs: field support cost, including relibility of
components, interconnection, servicing cost

• Solution: Early prototyping, Design for testability,

Programmability (like software design, using
VHDL, Verilog etc IEEE standards)
From design to implementation
to debug
Design considerations/constraints
Dynamic changes of hardware
design
 Radical change in logic design (Chap. 1.1)

(1) Automatic generation of logic circuits using

software tools.
(2) Versatile digital components (programmable,
FPGA, PLA--programmable logic array etc.)
(3) Design emphasis: shifting from detailed
implementation hardware to the software
specification.
Problems: software design, face same problems in
writing a program!
 The elements of modern design
Representation, circuit technology,
rapid prototyping
Digital hardware systems
 The art of design:
to design is to represent
 Semiconductor theory:
Why TSMC needs neno tech.?

• (1) Can you explain the function of the

following CMOS inverter, in terms of
Vin (gate voltage), and how the CMOS
will work in terms of fundamental semi-
conductor theory (electron or hole flow)?
What is the cause of flow of electrons or
holes?
 Neno(meter) technology
• 1 Angstrom = 10 to the -10 meters
• 1 Nano-meter = 10 to the -9 meters,
so, 1 nenometer is equivalent to 10
Hydrogen atoms

TSMC : industry leading 20/28 nm (Q4 2015, 16

nm) semiconductor process technology
Collaborates with Fujitsu on 28 nm process
CMOS inverter physical layers
 Semi-conductor theory II

(2) When the poly-silicon and diffusion layer

width is reduced by a factor of R, so are others.

Please answer what is the packing density

(gates/area)? power/gate, gate delay (speed) in
terms of R. Explain with simple explanations
using the following models, and make your
own assumptions.
 Scaling assumptions
**Voltage scaled by R, oxide thickness (T0) scaled
by R, then device current is scaled by R,
Depletion region width scaled by R, increase the
substrate doping, NA, by R
To simplify the condition:
• Case 1: The source-drain voltage, the width, the length, the
source-drain current flow, and the oxide thickness are ALL
reduced by R.
CMOS inverter physical layers
 Circuit theory
• Delay T is proportional to
Capacitor C and Impedance (Resistance) R
delay T = R*C
speed S is inversely proportional to T
R is proportional to length(L), and inversely
proportional to width(W) of resistor: L/W
C is proportional to area (A) divided by distance
(D)of two plates: A/D
 Basic scaling properties
• Parameter scaling factor
Dimension L 1/R
W 1/R
t0 (Oxide thickness) 1/R
Doping concentration R
Voltage 1/R
Current 1/R
(current is proportional to W/L*V2/t0 )
 The effect of scaling (k)

Packing density R2
Capacitance 1/R
Power/gate (VI) 1/R2
Chip power density 1
Gate delay, (CV/I) 1/R
Power/delay product 1/R3
Intro. VLSI: Carver Mead (Caltech)Lynn Conway
(Xerox Parc) 1980
CMOS inverter
CMOS inverter: black and white
representation
Transistors in row
Symmetrical arrangement of
transistors (FETs)
Basic design rule checking
Design rule checking
 Some example of DRC's in IC design
include:

• Active to active spacing

• Well to well spacing
• Minimum channel length of the transistor
• Minimum metal width
• Metal to metal spacing
• Metal fill density (for processes using CMP)
• ESD and I/O rules
• Antenna effect
Rules for design rule checking:
basic rules
Four bit counter: with flip-flops
Toggle cell stick diagram
A counter layout
Gate array for four-input CMOS
NOR gates
PLA layout
Reverse engineering: guess what
is this?
 Expected capabilities after this
course
• (1) Design (forward design)
• (2) Analysis (reverse engineering)
see the exam problem sets.
(3) Get to know how to build a chip or
computer, and the working environment of
chip/computer design companies.
(4) The world trend in hardware and
software integration.