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Semiconductor Chip Testing Fundamentals

The document discusses manufacturing defects in integrated circuits, defining key terms such as defects, faults, errors, and failures. It categorizes manufacturing defects into global and spot defects, explaining their causes and impacts on yield loss. The document emphasizes that while global defects can be minimized, controlling spot defects is more challenging and significantly contributes to yield loss.
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0% found this document useful (0 votes)
18 views15 pages

Semiconductor Chip Testing Fundamentals

The document discusses manufacturing defects in integrated circuits, defining key terms such as defects, faults, errors, and failures. It categorizes manufacturing defects into global and spot defects, explaining their causes and impacts on yield loss. The document emphasizes that while global defects can be minimized, controlling spot defects is more challenging and significantly contributes to yield loss.
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

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06/08/2025
19EC37E – FUNDAMENTALS OF SEMICONDUCTOR CHIP
TESTING

PRESENTED BY,
[Link] ANAND,
Assistant Professor (Senior Grade)/ ECE,
-National Engineering College, [Link], Kovilpatti.
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“ Manufacturing Defects in Integrated


Circuits (IC)

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Defect: unintended difference between the
implemented HW and its intended design
May or may not cause a system failure

Fault: representation of a defect at the abstracted


Defects, Faults, function level
and Errors
Defect X
Fault

Imperfections in
Imperfections in
the HW
the function
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 Error: Manifestation of a fault that results in


incorrect circuit (system) outputs or states
– Caused by faults
 Failure: Deviation of a circuit or system from
Defects, Faults, its specified behavior
and Errors – Fails to do what it should do
– Caused by an error

Defect --> Fault ---> Error ---> Failure

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 Processing defect: a short of b to ground


 Fault: signal b stuck-at logic 0

Example

Error: z has the wrong value if a = b = 1

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 Defect: a short to ground


 Fault: signal b stuck at logic 0

Example

 Error: z has the wrong value if a = b = 1


 But, if a = 0, fault exists, but no error!
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 Manufacturing Defects are classified into


 Global Defects (gross area defects)
 Spot Defects
 Global Defects: It termed as relatively large-scale defects,
Manufacturing such as scratches from wafer mishandling, large-area defects
from mask misalignment, and over- and under-etching.
Defects  Spot Defects: They are random local and small defects from
materials used in the process and from environmental
causes, mostly the result of undesired chemical and airborne
particles deposited on the chip during the various steps of
the process.

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 Both defect types contribute to yield loss.


 In well-controlled fabrication lines, gross-area defects can
be minimized and also eliminated.
 Controlling random spot defects is considerably more
Manufacturing difficult.

Defects  The yield loss due to spot defects is much greater than the
yield loss due to global defects.
 For large – area integrated circuits, the frequency of global
defects is independent of the die size, whereas the expected
number of spot defects increases with the chip area.

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 It is divided into several types according to their


location and they cause potential harm.
 Some causing missing patterns which may result
Spot - Defects in open circuits and some others cause extra
patterns that may result in short circuits.

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 These spot defects classified into
 Intralayer Defects
 Interlayer Defects
 Intralayer Defects: Occurs due to the particles deposited
during the lithographic process also known as
Photolithographic Defects.
Spot Defects  Examples of Intralayer Defects:
 Missing Metal Diffusion or
Polysilicon
 Extra Metal Diffusion or
Polysilicon

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 Interlayer Defects: Missing material in the vias


 Between two metal layers or between a metal
layer and polysilicon.
Spot Defects  Extra material between the substrate and metal or
between two separate metal layers.

 Intralayer Defects occurs due to dust particles.

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 Not all spot defects result in structural faults


 line breaks or short circuits.
 For a defect to cause a fault, it has to be large
enough to connect two disjoint conductors or to
disconnect a continuous pattern.
Spot Defects

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 A defect is any imperfection on the wafer, but


only those defects that affect the circuit operation
are called faults
 This causes the yield losses.
Defects

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Thank You

06/08/2025

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