J-K Flip-Flop
PRESENTED BY: MARYAM KHALID [F2024477001]
ESHA IMRAN ALISHA RAHMAN
PRESENTED TO: MS. HIRA YASEEN
DEPARTMENT OF PHYSICS
Introduction
• • A flip-flop is a bistable multivibrator used for
storing binary data (0 or 1).
• • The J-K Flip-Flop is the most versatile type of
flip-flop.
• • It overcomes the undefined state of the SR
Flip-Flop.
Truth Table of J-K Flip-Flop
Circuit Diagram
circuit diagram of the J-K Flip-Flop using NAND
gate:
Characteristic Equation
• Q(next) = JQ̅ + K̅Q
• Used in designing sequential circuits.
Clock signal:
• It is a timing signal.
• Use to provide sequence.
• Also called clock pulse.
Working:
• it decides when memory is used as input.
• Work as control input.
SR latch SR flip flop
Asynchronous(output depends on Synchronous( output is
input) controlled by clock)
Triggering:
It is condition when a flip-flop responds to inputs and
changes its output.
they only change state when triggered by the clock signal.
Types of triggering :
RACE AROUND CONDITION
•Normal Operation:
In a JK from 0 to 1 or 1 to 0)
on the active clock called
racing edge. Q=1,Q’ flip-
flop, when J=1 and K=1, the
output toggles (changes =0
Toggling:
• If the clock pulse is high (or
active) for a prolonged
period, the output will toggle
multiple times within that
single clock pulse
duration. This repeated
toggling is the "race around".
•Avoiding the Condition:
• Master-Slave JK flip-flop
• Shortening the duration of the clock
pulse tp than propagation delay
• Use edge triggring.
MASTER SLAVE
Use two flip-flops in series – Master and Slave
•Master responds to rising edge of clock.
•Slave responds to falling edge of clock.
•This setup ensures no change during the same
clock pulse.
Master slave :
Clock = 1: Master is active, slave is inactive.
•Inputs (J, K) are stored in master.
Clock = 0: Master is inactive, slave is
active.
•Slave copies the master's output
Timing Diagram
Applications
• • Used in counters (binary, ring, etc.)
• • Memory storage elements
• • Shift registers
• • Control systems and automation
Advantages
Versatile Functionality:
Acts as a Set, Reset, Toggle, and No Change flip-flop depending on inputs (J and K).Can be configured to perform like SR, T,
or D flip-flops.
Avoids Invalid State of SR Flip-Flop:
Unlike the SR flip-flop, the JK flip-flop does not suffer from the undefined or invalid condition when both inputs are HIGH.
Edge-Triggered Operation:
Works on clock edges (usually positive or negative edge), making it suitable for synchronous circuits.
Toggle Capability:
When both inputs J and K are 1, it toggles the output — useful in counters and frequency dividers.
Reliable Output:
Provides stable and predictable outputs if designed correctly with proper timing.
DISADVANTAGES
Complex Design:
Has a more complex circuit than SR or D flip-flops due to feedback and additional logic gates.
Timing Problems (Race Condition):
If clock pulse is too long, the output can toggle repeatedly when both J and K are 1 — this is known as a race-around
condition.
Requires Extra Logic to Avoid Race-Around;
Solving the race-around issue may need edge-triggered or master-slave configurations, increasing circuit size.
Higher Power Consumption;
The complexity and feedback circuitry lead to higher power usage than simpler flip-flops.
Not Ideal for All Applications;
In many modern digital circuits, simpler flip-flops like D flip-flops are preferred for ease of use and timing simplicity
Summary
• • J-K Flip-Flop is a universal flip-flop
• • Widely used due to its flexibility and
reliability
• • Key to designing counters and memory units
• THANK YOU