Design of Control
Unit
Introduction
A CPU can be considered as a collection of three major components:
Arithmetic logic unit (ALU)
Control unit (CU)
Register set.
The ALU performs arithmetic and logic operations on the data values
stored in registers, where the sequence of operations is controlled by the
CU.
The function of the CU is to control system operations by routing the
selected data items to the selected processing hardware of ALU at the
right time. A control unit’s responsibility is to activate the associated
processing hardware units by generating a set of signals that are
synchronized with a master clock. The inputs to the control unit are the
master clock, status information from the processing units and command
signals from the external devices like memory, I/O system. The outputs
produced by the typical control unit are the signals that activate the
processing units and responses to an external environment (such as
operation complete and operation aborted) due to exceptions (integer
overflow or underflow).
A control unit performs the following responsibilities:
Instruction interpretation
Instruction sequencing
Introduction
Instruction Interpretation:
During the interpretation phase, the control unit reads instructions from
the memory (using the PC register as a pointer). It then resolves the
instruction type and addressing mode, gets the necessary operands and
routes them to the appropriate functional units of the execution unit.
Required signals are then issued to the different units of ALU to perform
the desired operation and the results are routed to the specific
destination. Thus, this phase is done in “instruction decoding” step of
the instruction cycle.
Instruction Sequencing
During the sequencing phase, the control unit finds the address of the
next instruction to be executed and loads it into the PC. Thus, this phase
is done in “instruction fetch” step of the instruction cycle.
Primary Concept
The preliminary concepts forming the basis for control unit design are
the register transfer microoperations and their analytical descriptions.
The register transfer occurs under some predetermined control
condition(s), which is (are) generated by the control unit. Here we take
another example for further illustration.
If t = 0 and x = 1 then A 🡨B
else A 🡨D
where A, B and D are 4-bit registers.
Here, depending on the x and t values, 4-bit content of B or D register is
copied
to A register.
Such a selective register transfer microoperation can be expressed as
follows:
C: A 🡨 B
C’: A 🡨D [C’ indicates complement of C].
Where C = t’ . x and C’ = (t’ .x)’.
A hardware implementation for this transfer is shown in Fig..
The B register is selected by the MUX if condition C = 1; otherwise
register D is selected as source register.
Primary Concept
Design Method
Control units are designed in two different ways:
Hardwired approach
Microprogramming approach
When the control signals are generated using conventional sequential
logic design techniques, the control unit is said to be hardwired. The
sequential logic circuit generates specific sequences of control signals in
response to externally supplied instructions. Logic gates, flip flops,
decoders and other digital circuits are used to implement hardwired
control organization. As name suggests, if the
design has to be changed or modified, a hardwired control unit requires
changes in the wiring among the various components. Hardware control
unit is a conventional design technique.
In the microprogrammed approach, all control functions that can be
simultaneously activated are grouped to form control words stored in a
separate ROM memory called the control memory. From the control
memory, the control words are fetched one at a time and the individual
control fields are
routed to various functional units to activate their appropriate circuits.
The desired task is performed by activating these circuits sequentially.
Figure depicts the general structures of hardwired and microprogrammed
control units. Microprogrammed control unit is a modern technique.
Design Method
Comparison between Hardwired and Microprogramming
Theapproach
microprogramming approach is more expensive than hardwired
approach. In microprogramming approach, a control ROM memory is
needed. The main advantage of microprogramming is it provides a well-
structured control organization. Control signals are systematically
transformed into formatted words (microinstructions). With
microprogramming, many additions and changes are made by simply
changing the microprogram in the control memory, as the control signals
are embedded in a kind of two-level software called firmware.
A small change in the hardwired approach (due to design mistake, new
instruction to be added or new hardware component with higher speed
available) may lead to redesigning the entire system.
Now-a-days microprogramming is accepted as a standard tool to design
the control unit of a computer. For example, processors such as IBM 370,
PDP-11 and Intel 80 X 86 family have a microprogrammed control unit.
However, some olden day computers like Zilog’s 16-bit microprocessor
Z8000 still use a hardwired control unit.
Hardwired Control
The hardwired control Design
unit design includes the following summarized
steps:
1. State the task to be performed.
2. Suggest a trial processing section.
3. Devise a register-transfer description of the algorithm based on the
processing section outlined in the step 2.
4. Describe major characteristics of the hardware components to be used
in the processing section.
5. Establish the design of the processing section by providing necessary
control signals.
6. Provide a block diagram of the controller section.
7. Generate the state diagram of the controller section with different
control states.
8. Specify the characteristics of the hardware components to be used in
the controller section.
9. Give the complete design of the controller and draw a logic diagram of
the final circuit.
Multiplier Control Unit
Step 1 Statement of task to be performed
Implement a Booth’s multiplier to multiply two signed 4-bit numbers.
On each cycle of the booth algorithm, Q0 and Q-1 bits of multiplier will be checked on
the following parameters as follows:
When two bits Q0 and Q-1 1 are 00 or 11, we simply perform the arithmetic shift
right operation (ashr) to the partial product AC. And the bits of Q0 and Q - 1 is
incremented by 1 bit.
If the bits of Q0 and Q -1 is shows to 01, the multiplicand bits (M) will be added
to the A (Accumulator register). After that, we perform the right shift
operation to the A and Q bits by 1.
If the bits of Q0 and Q-1 is shows to 10, the multiplicand bits (M) will be
subtracted from the A (Accumulator register). After that, we perform the right
shift operation to the AC and Q bits by 1.
Multiplier Control Unit
Step 2 Suggest a trial processing section.
To design Booth’s multiplication method, the processing section is
proposed in the Fig..
As per Booth’s algorithm, the 4-bit register M will hold the multiplicand.
The multiplier Q register is 5-bit wide. Initially, the high-order 4-bit of
this register will hold the 4-bit multiplier. The least-significant bit of this
register is initialized with the fictitious 0.
The 4-bit adder/subtractor unit is used to perform the operations A + M
or A – M. The result produced by this hardware unit is always stored to
the 4-bit accumulator A. Here, the accumulated partial product stored in
(AQ) register pair is shifted right.
The L register is used to keep track of the iteration count. In the example
case, this register is initialized with decimal 4 and thus L is 3-bit in
length and decremented by 1 after the completion of each iteration.
Thus, the algorithm terminates when L reaches decimal 0. When L equals
to decimal 0 (termination of algorithm), the high- and low-order 4 bits of
the final product are found in the
registers A and Q, respectively.
The 4-bit data buses - Inbus and Outbus, are used to transfer data into
and out of the processing section respectively.
Multiplier Control Unit
Multiplier Control Unit
Step 3 Devise a register-transfer description of the algorithm based on
the processing section outlined in the step 2.
For 4 X4 Booth’s multiplication algorithm, a register transfer description
is devised next.
Q [0: –1] is used to indicate the low-order 2 bits of the Q register (Initially
Q[0] indicates the lsb of Q register and Q[–1] indicates a fictitious 0).
Similarly, Q[3:0] indicates the high-order 4 bits of the Q register. The last
step, Go to HALT, introduces an infinite loop after the algorithm is
completed.
Registers: M[4], A[4], Q[5], L[3];
Buses: Inbus[4], Outbus[4];
START A 🡨0, M 🡨Inbus, L🡨4
Q[3:0] 🡨Inbus, Q[–1] 🡨0;
LOOP If Q[0:–1] = 01 then go to ADD
If Q[0:–1] = 10 then go to SUB
Go to RSHIFT;
ADD A 🡨 A + M;
Go to RSHIFT;
SUB A 🡨 A – M;
RSHIFT ASR (AQ), L 🡨L–1;
If L =/ 0 then go to LOOP
Output = A;
Output = Q[3:0];
HALT Go to HALT;
Multiplier Control Unit
Step 4 Describe major characteristics of the hardware components to be
used in the processing section.
The processing section contains three main elements:
4-bit adder/subtarctor.
General-purpose registers.
Tri-state buffers.
The operational characteristics of these three elements are provided in
Fig. 6.4. By introducing the proper values to control inputs C, L, R and D,
four operations (clear, parallel load, right shift and decrement) can be
performed. A clock circuit synchronizes all these operations.
The 4-bit adder/subtractor can be implemented using a 4-bit parallel
adder chip and four XOR gates.
To build a general-purpose register, standard flip-flops and gates can be
used.
The tri-sate buffers are used to control the data transfer to the outbus.
Multiplier Control Unit
Multiplier Control Unit
Step 5 Establish the design of the processing section by providing
necessary control signals.
There are 10 control signals required: C0, C1, C2, C3, C4, C5, C6, C7, C8,
C9 and their tasks are provided next. The micro-operations A 🡨0, M
🡨Inbus, L 🡨4 will be executed when C0, C1, C2 are held high.
Similarly, other micro-operations are performed by activating proper
signals. Though, the signals’ tasks are self-explanatory. A detail logic
diagram of the processing section along with various control signal
points is shown in Fig..
In the diagram, a total of 8 tri-state buffers are needed, out of which a
set of 4 buffers are controlled by C8 and another set of 4 buffers are
controlled by C9. Though two buffers are shown in Fig. 6.5, one is
controlled by C8 and other is controlled by C9.
Multiplier Control Unit
Multiplier Control Unit
Multiplier Control Unit
Step 6 Provide a block diagram of the controller section.
The processing section intermediately generates three outputs Q[0], Q[–
1] and Z. When the content of the L register becomes 0, then Z register is
set to 1. These outputs are status outputs and are used as inputs to the
controller to allow the controller to decide the next step of the algorithm.
With this information a block diagram for the controller section can be
generated, as shown in the Fig. 6.6.
Multiplier Control Unit
Step 7 Generate the state diagram of the controller section with different
control states.
The controller has 5 inputs and 10 control outputs. The clock input is
used to synchronize the controller’s activities.
The Reset input is asynchronous input used to reset the controller so that
a new computation can start.
The controller must initiate a set of micro-operations in a specified
sequence controlled by the clock input. Thus, it is recognized as a
sequential logic circuit. The state diagram for the Booth’s multiplier
controller is shown in the Fig. 6.7.
Initially, the controller is in the state T0. At this time the control signals
C0, C1 and C2 are generated at high state. Thus, the operations A 🡨0, M
🡨Inbus and L🡨 4 are performed.
The controller then moves to the state T1 in the next clock cycle to
perform the operation Q[3:0] 🡨Inbus and Q[–1] 🡨0.
The controller moves to the state T9 only when a computation is
completed and the controller stays in that state infinitely until a Reset
input forces the controller to switch to the state T0 and a new
computation step starts.
Multiplier Control Unit
The states are generated in the state diagram according to the following
rules:
If the two or more micro-operations are independent of each other and
can be completed within one clock cycle, they are grouped into one state.
For example, micro-operations A 🡨0, M 🡨Inbus and L 🡨4 are independent
to each other. That is why they are executed in one clock period.
If these microoperations cannot be performed within the selected T0
clock period, then either clock period duration needs to be increased or
the micro-operations have to be divided into a sequence of micro-
operations.
Generally a new state is introduced for conditional testing. For example,
the Conditional testing of the bit pair Q[0] Q[–1] introduces the new state
T2 in Fig. 6.7.
There are 10 states in the controller state diagram. Ten non-overlapping
timing signals (T0 to T9) must be generated for the controller to perform
the Booth’s algorithm. But, only one will be high for a clock pulse.
Multiplier Control Unit
Multiplier Control Unit
Step 8 Specify the characteristics of the hardware components to be
used in the controller section.
Since minimum 10 clock cycles (periods) are needed for 10 states in the
controller, a mod-16 counter and a 4-to-16 decoder are used to generate
the clock periods and to select one of the control signals at the
appropriate state respectively. The characteristic of the mod-16 counter
is discussed in the Fig. 6.8.
Step 9 The controller and its logic diagram are shown in the Fig. 6.9. The
main
component of this design is the sequence controller (SC) hardware, which
sequences the controller as indicated in the state diagram in Fig. 6.7.
The truth table of SC is derived from the controller’s state diagram and is
shown in Table 6.1.
Multiplier Control Unit
Multiplier Control Unit
Multiplier Control Unit
For example, consider the logic involved in deriving the first entry of the
SC truth table. Observe that the mod-16 counter is loaded with the
specified external data if the counter control inputs C and L are 0 and 1
respectively. From the controller’s state diagram, it can be observed that
if the present control state is T2 (counter output = 0010) and if the bit
pair inspected is 00 (i.e., Q[0] Q[–1] = 00) then the next state will be T5.
When these input conditions occur, the counter must be loaded with
external data value 0101 (When counter output = 0101, then T5 =1).
Therefore, the SC generates load (L) = 1 and d3 d2 d1 d0 = 0101. Using
the same reasoning, the last entry of the SC truth table is obtained. From
the controller’s state diagram, it can be observed that if the present
state is T9, the next control state will be same T9 (it stays in the infinite
loop). The SC must generate the outputs load (L) =1 and d3 d2 d1 d0 =
1001 to obtain the desired state sequence. Similarly, other entries of the
SC truth table are derived.
The counter will automatically count up in response to the clock pulse
(because the enable input E is fixed with 1), when the counter load
control input L = 0. In other words, the sequential execution flow will be
there when load input (L) = 0. Such normal sequencing activities are
desirable in the following situations:
Present state is: T0, T1, T4, T5, T7, or T8.
Present state is: T2 and Q[0] Q[–1] = 01.
Present state is: T6 and Z = 1.
Multiplier Control Unit
These results suggest that the SC should not affect the counter load
control input L. Hence these possibilities are excluded from the SC truth
table. The SC must exercise control only when there is a need for the
counter to deviate from its normal counting sequence.
CPU Hardwired Control Unit The general CPU hardwired control unit is
depicted in Fig. 6.10. The inputs to the control unit are content of
instruction register (IR), the clock signal, the status (flag) and control
signals. Consider, the instruction register (IR). The control unit will
perform different functions for different instructions. There must be a
unique logic input for each op-code to simplify the control unit logic. In
order to perform this function, a decoder is used which takes an encoded
input and produces a single output. To synchronize all micro-operations,
a clock unit is used which issues a repetitive sequence of pulses. The
clock cycle time must be long enough to allow the propagation of signals
along data paths and through processing units. The control unit
generates different control signals at different time units within a single
instruction cycle. For this reason, a counter is used as input to the
control unit to generate different timing states T1, T2, T3 and so on for
different control signals. At the end of the instruction cycle, the control
unit must reinitialize the counter at T1 using special Reset signal.
Multiplier Control Unit
Microprogrammed Control Unit
Microprogramming is a modern concept used for designing a control unit.
It can be used for designing control logic for any digital system. In a
microprogrammed control unit, the control signals are stored as bit
patterns called control word in a read only memory called controlled
memory, inside the control unit. Each instruction needs a specific set of
microoperations and these microoperations are executed when the
corresponding control signals are made active. Each control word in the
control memory contains signals to activate one or more micro-
operations. When these words are retrieved in a sequence, a set of
micro-operations are activated that will complete the desired task.
Hence, The philosophy of microprogramming is based on ‘reading stored
control patterns’.
Like conventional program, retrieval and interpretation of the control
words are done. The instructions of a CPU are stored in the main memory.
They are fetched and executed in a sequence. The CPU can perform
different functions simply by changing the instructions stored in the main
memory.
Similarly, the control unit can execute a different control operation by
changing the contents of the CM. Hence, the microprogrammed approach
offers greater flexibility than its hardwired counterpart, since this
approach is based on the programming concept giving an easy way for
altering the contents of the CM.
Microprogrammed Control Unit
Usually, all microinstructions of microprogrammed have three important
fields:
Control field
Next-address field
Condition for branching.
A control memory in addition to the conventional main memory is used in
the microprogramming approach. Thus, it is desired to give more
emphasis on minimizing the length of the microinstruction. The length of
the microinstruction decides the size of the control memory, as well as
the cost involved with this approach.
The following factors are directly involved with the length of a
microinstruction:
▪ How many micro-operations can be activated simultaneously
(the degree of parallelism).
▪ The control field organization.
▪ The method by which the address of the next microinstruction
is specified.
Several micro-operations can be executed simultaneously when a single
microinstruction with a common op-code is specified for all micro-
operations executed in parallel. This allows short microprograms to be
written but the length of microinstruction increases, whenever there is a
need for parallelism. Similarly, short microinstructions have limited
capability in expressing parallelism. Since massive parallelism is not
possible using short microinstructions, the overall length of a
microprogram written using these instructions will increase.
Microprogrammed Control Unit
Control Field Organization:
There are various ways to organize control information. A simple way to organize
the control field would be to have 1 bit for each control line that controls the
processing unit, allowing full parallelism, and there is no need for decoding the
control field.
However, this method cannot use the control memory efficiently when it is
impossible to invoke all control operations simultaneously.
Consider the example shown in Fig.. Assume there are four registers A, B, C and D
whose contents are transferred to the destination register R when the appropriate
control line is activated:
C0: R🡨A
C1: R 🡨B
C2: R 🡨C
C3: R 🡨D
Since there is only one destination register R, it is not possible to allow more than
one transfer at any given time. If one bit is allocated for each control in the control
field, the result will appear as shown next:
This method of organizing control
fields is known as unencoded
format.
Microprogrammed Control Unit
Control Field Organization:
In the previous format, there are only five valid binary patterns. However, five
distinct binary patterns can be represented by using only 3 bits according to the
basic switching theory. Such an arrangement is illustrated in Fig.. The control
information is encoded into a 3-bit field, and a decoder is needed to get the actual
control information, in Fig. . The relationship between the encoded and the actual
control information is specified as follows:
This way of organizing the control field is known as encoded format method, which
specifies to a short control field and short microinstructions. One extra hardware
element, namely decoder is needed for such a reduction. Therefore, a compromise
must be made.
Microprogrammed Control Unit
Control Field Organization:
Fifteen control lines can be specified in a fully unencoded form as shown next:
In the first and second cases, the sizes of the control field are 16 and 4 bits,
respectively. However, the second approach needs a 4-to-16 decoder to generate
the actual control signals. Thus, the control information is given by a partial
encoding, as a measure of compromise and is shown next:
The control signals are partitioned into disjoint groups of control fields, so two
signals of different groups can be enabled in parallel. For the above example, the
control signals are partitioned into two groups as:
Group 1: C1 C2 C3 C4 C5 C6 C7.
Group 2: C8 C9 C10 C11C12 C13 C14 C15.
With the above grouping, C8 can be activated simultaneously with C1 or C2 but not
C1 and C2. Using one 3-to-8 and one 4-to-16 decoders, the actual control signals
are generated. In the last case, the control field requires 7 bits E0 to E6. This
technique is mixed one which lies between the unencoded and fully encoded
approaches.
Microprogrammed Control Unit
Horizontal and Vertical
Based on the
Microprogramming
length of microinstructions, the microprogramming method is either
horizontal or vertical.
Having an individual bit for each control signal in the microinstruction format is
known as a
horizontal microinstruction, as shown in Fig. 6.13. The unencoded method,
discussed above, is usually followed in horizontal organization. Each bit in
microinstruction activates one control signal. Several control signals can be
simultaneously generated by a single microinstruction. The length ofthe
microinstruction is large. Horizontal microinstructions have the following general
attributes:
Long formats.
Ability to express a high degree of parallelism.
Very little encoding of the control information.
In the IBM 360/model 50, the microinstructions used in control unit follow horizontal
format.
In a vertical microinstruction , a single field can produce an encoded sequence. The
encoded technique is followed in this organization. The vertical microprogram
technique takes more time for generating the control signals due to the decoding
time and also more microinstructions are needed. But the overall cost is less since
the microinstructions are small in size. The horizontal microprogram releases faster
control signals but the control memory size is huge due to increased word length.
Thus, the vertical microinstructions are characterized by:
Short formats.
Limited ability to express parallel microoperations.
Considerable encoding of the control information.
Structure of Microprogramming Control Unit
The architecture of a typical modern microprogrammed control unit is shown in Fig.
which consists of various components summarized below.
Control Memory Buffer Register (CMBR) The function of CMBR is same as the MBR
(memory buffer register) of the main memory. It is basically a latch and acts as a
buffer for the microinstructions retrieved from the CM. Typically, each
microinstruction has three fields as:
Condition Select Branch Address Control Function
The condition select field selects the external condition to be tested. The output of
the MUX will be 1, if the selected condition is true. The MPC will be loaded with the
address specified in the branch address field of the microinstruction, because the
output of the MUX is connected to the load input of the microprogram counter
(MPC). However, the MPC will point to the next microinstruction to be executed, if
the selected external condition is false. Thus, this arrangement allows conditional
branching.
The control function field of the microinstruction may hold the control information in
an encoded form which thus may require decoders.
Microprogram Counter (MPC) The task of MPC is same as the PC (program counter)
used in the CPU. The address of the next microinstruction to be executed is held by
the MPC. Initially, it is loaded from an external source to point to the starting
address of the microprogram to be executed. From then on, the MPC is incremented
after each microinstruction fetch and the instruction fetched is transferred to the
CMBR. However, the MPC will be loaded with the contents of the branch address
field of the microinstruction that is held in the CMBR, when a branch instruction is
encountered.
Structure of Microprogramming Control Unit
Structure of Microprogramming Control Unit
External Condition Select MUX Based on the contents of the condition select field of
the microinstruction, this MUX selects one of the external conditions. Therefore, the
condition to be selected must be specified in an encoded form. Any encoding leads
to a short microinstruction, which implies a small control memory; hence the cost is
reduced. Suppose two external conditions X1, X2 are to be tested; then the
condition-select and actions taken are summarized next:
Condition select Action taken
00 No branching
01 Branch if X1 =1
10 Branch if X2 =1
11 Always branching (unconditional branching)
The multiplexer has four inputs V0, V1, V2, V3 where Vi is routed to the
multiplexer’s output when the condition select field has decimal equivalent i. Hence
we require V0 = 0, V1 = X1, V2 = X2, V3 = 1 to control the loading of
microinstruction branch addresses into MPC.
Microprogramming Control
Example: The design
Unit
of a typical microprogrammed control unit is discussed now.
Consider
the implementation of a microprogrammed control unit for the 4 X 4
Booth’s multiplication. First step will be writing of the microprogram in a symbolic
form, then next task will be generating of control signals and architecture of the
control unit, and lastly we will give the microprogram in binary for 4 X 4 Booth’s
multiplication. The symbolic microprogram for 4 X 4 Booth’s multiplication
is as follows: Control Memory Control word
Address
0 Start A 🡨0, M 🡨Inbus, L 🡨4
1 Q[3:0] 🡨Inbus, Q[–1] 🡨0;
2 LOOP If Q[0: –1] = 01 then go to ADD
3 If Q[0: –1] = 10 then go to SUB
4 Go to RSHIFT;
5 ADD A 🡨A + M;
6 Go to RSHIFT;
7 SUB A🡨 A – M;
8 RSHIFT ASR (AQ), L🡨 L–1;
9 If Z = 0 then go to LOOP
10 Output = A;
11 Output = Q[3:0];
12 HALT Go to HALT;
Microprogramming Control
In this task, three
Unit
conditions, Q[0] Q[–1] = 01, Q[0]Q[–1] = 10 and Z = 0, are tested.
Here, Z corresponds to the L register. When L not equal to 0, Z is reset to 0,
otherwise Z is set to 1. These three conditions are applied as inputs to the condition
select MUX.
Additionally, to take care of no-branch and unconditional-branch situations, logic 0
and logic 1 are applied as data inputs to this MUX, respectively. Therefore, The MUX
is able to handle five data inputs and thus must be at least an 8:1. The size of the
condition select field must be 3 bits in length. With this design, the condition select
field may be interpreted as below:
Condition select Action taken
000 No branching
001 Branch if Q[0] =0 and Q[–1] =1
010 Branch if Q[0] =1 and Q[–1] = 0
011 Branch if Z =0
100 Unconditional branching
With these details, the size of the control word is calculated as follows:
Size of a control word=size of the condition select field + size of the branch address
field + number of control functions
= 3 + 4 + 10
= 17 bits.
Hence, the sizes of the CMDB and CM are 17 bits and 13 X 17, respectively. The
complete hardware organization of the control unit and control signals is shown in
Fig..
Microprogramming Control
C0 : A 🡨0
Unit
C1 : M 🡨Inbus
C2 : L ¨ 4
C3 : Q[3:0] 🡨Inbus, Q[–1] 🡨0
C4 : F = l + r
C’4 : F = l – r
C5 : A 🡨F
C6 : ASR (AQ)
C7 : L🡨 L – 1
C8 : Outbus = A
C9 : Outbus = Q[3:0]
Microprogramming Control
Finally, the
Unit
generation of binary microprogram stored in the CM will be discussed.
There exists a control word for each line of the symbolic program listing.
For example, consider the first line (0th) of the symbolic listing program mentioned
previously. This instruction, being a simple load instruction, introduces no
branching. Therefore, the condition-select field should be 000. Thus, the contents of
the branch address field are irrelevant. However, without any loss of generality, the
contents of this field can be reset to 0000. For this instruction, three micro-
operations C0, C1 and C2 are activated. Therefore, only the corresponding bit
positions in the control function fields are set to 1.
This results in the following binary microinstruction:
Condition select Branch address Control function
000 0000 1110000000
The binary microinstruction corresponding to third line of the symbolic
microprogram does not activate any micro-operation. But, it branches to 5th
location after checking one condition (Q[0: –1] = 01). So, the condition-select field
should be 001 and the branch address will be 0101. Therefore the complete binary
microinstruction corresponding to this instruction is as follows:
Condition select Branch address Control function
001 0101 0000000000
Microprogramming Control
Continuing in this
Unit
way, the complete binary microprogram for 4 X 4 Booth’s
multiplier can be produced, as in the Table.
Address
0 Start A 🡨0, M 🡨Inbus, L 🡨4
1 Q[3:0] 🡨Inbus, Q[–1] 🡨0;
2 LOOP If Q[0: –1] = 01 then go to
ADD
3 If Q[0: –1] = 10 then go to
SUB
4 Go to RSHIFT;
5 ADD A 🡨A + M;
6 Go to RSHIFT;
7 SUB A🡨 A – M;
8 RSHIFT ASR (AQ), L🡨 L–
1;
9 If Z = 0 then go to LOOP
10 Output = A;
11 Output = Q[3:0];
12 HALT Go to HALT;
CPU Microprogramming Control Unit
Here, we want to design microprogrammed control unit for a basic accumulator-
based CPU as shown in Fig..
This CPU consists of a data processing unit (DPU) designed to execute the set of 10
basic single-address instructions listed in Table. The instructions are assumed to be
fixed length and to execute on data words of the same fixed length, say 32 bits. The
function of control unit (CU) is to manage the control signals linking the CU to the
DPU, as well as the control signals between the CPU and the external memory M. In
order to design the CU, first we have to identify the relevant control actions (micro-
operations) needed to process the given instruction set using the hardware from
Fig. 6.17. The instruction execution behavior of the CPU is shown in Fig. 6.18 using a
flowchart. All instructions require a common instruction-fetch phase, followed by an
execution-phase that varies with each instruction type. The content of the program
counter (PC) is copied to the memory address register (AR) in the fetch phase. A
memory read operation is then executed, which transfers the instruction word I to
memory data register (DR); that is expressed by DR ¨ M(AR). Op-code of I is
transferred to the instruction