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CPU Architecture and Operations Tutorial

The document contains a tutorial with multiple questions related to computer architecture, including topics such as bus organized CPU, control words, micro-operations, stack operations, infix and reverse polish notation conversions, addressing modes, and FIFO memory operations. Each question requires specific calculations or formulations based on given scenarios and examples. The tutorial aims to enhance understanding of fundamental concepts in computer systems and architecture.

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Naman Singh
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7 views13 pages

CPU Architecture and Operations Tutorial

The document contains a tutorial with multiple questions related to computer architecture, including topics such as bus organized CPU, control words, micro-operations, stack operations, infix and reverse polish notation conversions, addressing modes, and FIFO memory operations. Each question requires specific calculations or formulations based on given scenarios and examples. The tutorial aims to enhance understanding of fundamental concepts in computer systems and architecture.

Uploaded by

Naman Singh
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Tutorial-Unit-3

Tutorial
Q1:A bus organised CPU has 16 registers with 32 bits in each,
an ALU and a destination decoder.
A. How many multiplexers are there in the A bus and what is
the size of each multiplexer?
B. How many selection inputs are needed for MUX A and
MUX B?
C. How many inputs and outputs are there in the decoder?
D. How many inputs and outputs are there in the ALU for data
,including input and output carries?
E. Formulate a control word for the system assuming that the
ALU has 35 operations.
Q2: Specify control word
A.R1 R2+R3
B. R4 R4
C. R5 R5-1
D.R6 Shl R1
E. R7 input
Q3:Determine the micro-operations that will be
executed in the processor, when the following
14-bit control words are applied.
a. 00101001100101
b.00000000000000
c. 01001001001100
d.00000100000010
e.11110001110000
Q4:

Let SP=000000 in the stack. How many items are there in the stack if
a. Full=1 and Empty=0?
B. . Full=0 and Empty=1?
Q5:Convert infix to reverse polish notation
a. A*B+C*D+E*F
b.A*B+A*(B*D+C*E)
c. A+B*[C*D+E*(F+G)]
d.X=A*[B+C*(D+E)]/F*(G+H)
Q6:CONVERT arithmetic expressions from
reverse polish to infix notation.
• A. ABCDE+*-/
• [Link]*/-+
• [Link]*/D-EF/+
• [Link]+*+*+*
Q7:An instruction is stored at location 300 with
its address field at location 301. The address
field has the value 400. A processor register R1
contains the number 200. Evaluate the effective
address if the addressing mode of the
instruction is (a)Direct (b)Immediate (c)relative
(d)register indirect (e)Index with R1 as the index
register.
• (a)400
• (b)301
• (c)702
• (d)200
• (e)600
Q8:A two-word instruction is stored in memory at
an address designated by the symbol W. The
address field of the instruction (stored at W+1) is
designated by symbol Y. The operand used during
the execution of the instruction is stored at an
address Z. An index register contains the value X.
state how Z is calculated from the other addresses
if the addressing mode of the instruction is
(a)Direct, (b)Indirect, (c)relative,(d) indexed
Q9: The memory unit of a computer has 256K
words of 32 bits each. The computer has an
instruction format with four fields-an operation
code field, a mode field to specify one of seven
addressing modes, a register address field to
specify one of 60 processor registers and a
memory address. Specify the instruction format
and the number of bits in each field if the in
instruction is in one memory word.
Q10: Show how a fifo memory operates with
three counters . A write counter WC holds the
address for writing into memory. A read counter
RC holds the address for reading from memory.
An available storage counter ASC indicates the
number of words stored in FIFO. ASC is
incremented for every word stored and
decremented for every value that is retrieved.
Q11:A memory stack is organised such that SP
always point at the next empty location on the
stack. This means that SP can be initialized to
4000 and the first item in the stack is stored in
location 4000. List the micro-operations for the
push and pop operations.

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