THIẾT KẾ ALU 8
BIT
1. Thành viên nhóm:
Nội Dung Thuyết Trình
Tổng quan về ALU 01 03 MPLS
Logic và VPN
Synthesis VPN
Design code và
Testbench 02 04 Physical Design VPN
I. Tổng quan về ALU
CPU
Cộng,
Register trừ,…
ALU
Control And,
Unit Or,
Xor…
II. Design code và Testbench
1. Design Code
2. Testbench
III. Logic Synthesis
1. Design Compiler (process)
1. Design Compiler (report)
1. Design Compiler (report)
1. Design Compiler (report)
1. Design Compiler (report)
2. Formality (verification)
2. Formality (verification)
2. Formality (result)
IV. Physical Design
1. IC Compiler II (Setup)
1. IC Compiler II (Setup)
%icc2_shell>> read_verilog -top ALU_8bit design_mapped.v
1. IC Compiler II (Setup)
1. IC Compiler II (Initialize floorplan)
%icc2_shell>> initialize_floorplan -core_utilization 0.6 -core_offset {5}
1. IC Compiler II (Initialize floorplan)
%icc2_shell>> create_placement -floorplan
1. IC Compiler II (Initialize floorplan)
%icc2_shell>> legalize_placement
1. IC Compiler II(Place pins)
%icc2_shell>> set_block_pin_constraints -self -
allowed_layers {M3 M4 M5 M6} -pin_spacing_distance 2
%icc2_shell>> place_pins -self
1. IC Compiler II(Create power ring, mesh, and straps)
%icc2_shell>> source -echo ./scripts/[Link]
1. IC Compiler II (Create power ring, mesh, and straps)
%report_timing -max_paths 5 check_pg_drc -ignore_std_cells
1. IC Compiler II(Create power ring, mesh, and straps)
check_pg_connectivity -check_std_cell_pins none check_pg_missing_vias
1. IC Compiler II(Placement)
1. IC Compiler II(Placement)
1. IC Compiler II(Placement)
report_design -summary
1. IC Compiler II(Placement)
1. IC Compiler II(Placement)
check_design -checks pre_placement_stage
1. IC Compiler II(Placement)
After completing the step of placement step, some reports are
generated to compare the results pre-placement and post-placement.
check_legality -verbose
1. IC Compiler II(Placement)
report_timing -nosplit -transition_time -capacitance input_pins -nets -derate-delay_type max -path_type
full_clock_expanded voltage -significant_digits 4 -nworst 1 -physical -max_paths 100
1. IC Compiler II(Placement)
1. IC Compiler II(Clock tree synthesis)
1. IC Compiler II (Clock tree synthesis)
1. IC Compiler II (Clock tree synthesis)
1. IC Compiler II (Clock tree synthesis)
check_legality -verbose
1. IC Compiler II(Routing)
check_design -checks pre_route_stage
1. IC Compiler II (Routing)
compute_clock_latency -verbose
1. IC Compiler II (Routing)
1. IC Compiler II (Routing)
1. IC Compiler II (Routing)
compare the results of pre route and post route.
1. IC Compiler II (Routing)
1. IC Compiler II (Routing)
1. IC Compiler II (Routing)
1. IC Compiler II (Routing)
1. IC Compiler II (Routing)
check_routes
1. IC Compiler II (Signoff)
1. IC Compiler II (Signoff)
remove_stdcell_fillers_with_violation
1. IC Compiler II (DRC)
To check DRC in IC Compiler II, external tools are used such as IC Validator (ICV).
After setting up ICV in ICC2, run “signoff_check_drc” command to check DRC for the design.
1. IC Compiler II (Layout versus Schematic Check)
check_lvs -nets [get_nets] -checks {short open} -check_child_cells true report_floating_pins true -open_reporting detailed
2. Formality
2. Formality