Basic Assembly Language in RISC-
V Architecture
By [Link]
July 5th
Introduction to Assembly Language
• Low-level, human-readable form of machine
instructions
• Architecture-specific (e.g., RISC-V)
• Direct control over hardware behavior
What is RISC-V?
• RISC-V (pronounced “risk-five”) is an open standard Instruction Set
Architecture (ISA) based on Reduced Instruction Set Computing (RISC)
principles. It defines how software communicates with hardware at the
instruction level.
Features :
– Open-source, modular, and extensible ISA
– Developed at UC Berkeley (2010)
– Supports RV32I, RV64I, RV128I
– Extensible with optional modules (M, F, D, A, C, V)
RISC-V Register Set
• x0: zero – Always 0
• x1: ra – Return address
• x2: sp – Stack pointer
• x5-x7: t0-t2 – Temporaries
• x10-x17: a0-a7 – Arguments/Return values
• x8-x9, x18-x27: s0-s11 – Saved registers
• x28-x31: t3-t6 – Temporaries
RISC-V Instruction Formats
• R-Type: Arithmetic (add, sub)
• I-Type: Immediate and loads
• S-Type: Stores
• B-Type: Branching
• U-Type: Upper immediates (LUI, AUIPC)
• J-Type: Jumps (JAL)
RISC-V RV32I Instruction Set Summary
R-type: Register type
Instruction Description
add rd, rs1, rs2 Add
sub rd, rs1, rs2 Subtract
sll rd, rs1, rs2 Shift left logical
slt rd, rs1, rs2 Set less than (signed)
sltu rd, rs1, rs2 Set less than (unsigned)
xor rd, rs1, rs2 Bitwise XOR
srl rd, rs1, rs2 Shift right logical
sra rd, rs1, rs2 Shift right arithmetic
or rd, rs1, rs2 Bitwise OR
and rd, rs1, rs2 Bitwise AND
RISC-V RV32I Instruction Set Summary
I-Type: Immediate and Loads
Instruction Description
addi rd, rs1, imm Add immediate
slti rd, rs1, imm Set less than immediate (signed)
sltiu rd, rs1, imm Set less than immediate (unsigned)
xori rd, rs1, imm XOR immediate
ori rd, rs1, imm OR immediate
andi rd, rs1, imm AND immediate
slli rd, rs1, shamt Shift left logical immediate
srli rd, rs1, shamt Shift right logical immediate
srai rd, rs1, shamt Shift right arithmetic immediate
lb rd, imm(rs1) Load byte
lh rd, imm(rs1) Load halfword
lw rd, imm(rs1) Load word
lbu rd, imm(rs1) Load byte unsigned
lhu rd, imm(rs1) Load halfword unsigned
jalr rd, rs1, imm Jump and link register
RISC-V RV32I Instruction Set Summary
S-Type: Store type
Instruction Description
sb rs2, imm(rs1) Store byte
sh rs2, imm(rs1) Store halfword
sw rs2, imm(rs1) Store word
B-Type: Branch type
Instruction Description
beq rs1, rs2, imm Branch if equal
bne rs1, rs2, imm Branch if not equal
blt rs1, rs2, imm Branch if less than (signed)
bge rs1, rs2, imm Branch if greater or equal
(signed)
bltu rs1, rs2, imm Branch if less than (unsigned)
bgeu rs1, rs2, imm Branch if greater or equal
(unsigned)
RISC-V RV32I Instruction Set Summary
U-Type: Upper Immediate type
Instruction Description
lui rd, imm Load upper immediate
auipc rd, imm Add upper immediate to PC
J-Type: Jump type
Instruction Description
jal rd, imm Jump and link
Arithmetic Instructions
Instruction Type Operation Example
add R-Type Add reg + reg add t2, t0, t1
sub R-Type Sub reg - reg sub t2, t0, t1
Add reg +
addi I-Type addi t1, t0, 5
immediate
Set if less than
slt R-Type slt t2, t0, t1
(signed)
Set if less than imm
slti I-Type slti t1, t0, 5
(signed)
Set if less than
sltu R-Type sltu t2, t0, t1
(unsigned)
Set if less than imm
sltiu I-Type sltiu t1, t0, 1
(unsigned)
Memory Instructions
Type Operation Instruction Width Sign Extension Use Case
I-Type Load lw 32-bit N/A Load word from
memory
I-Type Load lb 8-bit Signed Read signed byte
I-Type Load lbu 8-bit Unsigned Read unsigned
byte
I-Type Load lh 16-bit Signed Read signed
halfword
I-Type Load lhu 16-bit Unsigned Read unsigned
halfword
S-Type Store sw 32-bit N/A Store word
S-Type Store sb 8-bit N/A Store byte
S-Type Store sh 16-bit N/A Store halfword
Control Flow
Instruction Type Purpose Jumps If...
beq B-Type Branch if equal rs1 == rs2
bne B-Type Branch if not equal rs1 ≠ rs2
blt B-Type Branch if less than rs1 < rs2
(signed)
Branch if greater/equal
bge B-Type (signed) rs1 ≥ rs2
bltu B-Type Branch if less than rs1 < rs2 (unsigned)
(unsigned)
Branch if greater/equal
bgeu B-Type (unsigned) rs1 ≥ rs2 (unsigned)
jal J-Type Unconditional jump Always
(with link)
jalr I-Type Jump to address in Always
register
Sample Program: Sum of Two Numbers
• li a0, 10
• li a1, 20
• add a2, a0, a1 # a2 = 30
Loop Example (Sum 1 to 10)
• li t0, 1 #i=1
• li t1, 10 # limit
• li t2, 0 # sum = 0
• loop:
• add t2, t2, t0 # sum += i
• addi t0, t0, 1 # i++
• bne t0, t1, loop
Function Call (Simple Sum)
• # Caller
• li a0, 5
• li a1, 6
• call sum
• # Callee
• sum:
• add a0, a0, a1
• ret
Memory and Stack
• Little-endian
• Stack grows downward
• Stack frame for function calls
Instruction Decoding (R-Type)
• assign opcode = instr[6:0];
• assign rd = instr[11:7];
• assign funct3 = instr[14:12];
• assign rs1 = instr[19:15];
• assign rs2 = instr[24:20];
• assign funct7 = instr[31:25];
Tools and Use in DV
• spike – ISA Simulation
• objdump – Disassembly
• QEMU – Emulation
• GDB – Debugging
• Verilator – RTL Simulation
• Used to debug RTL with assembly traces
Summary
• RISC-V: Clean, extensible ISA
• Easy to learn assembly syntax
• Needed for DV, firmware, architecture
• Understand registers, memory, function calls,
waveforms