Simple FM Slope Detector

The output voltage of the tank circuit is then

applied to a simple diode detector of an RC load
with proper time constant.

This detector is identical to the AM diode detector.

Even though the slope detector circuit is simple it
has the following drawbacks.
Drawbacks of Slope Detector
(i) It is inefficient.
(ii) It is linear only over a limited frequency range.
(iii) It is difficult to adjust as the primary and secondary winding of the transformer must be tuned to slightly different
frequencies.
Advantages of Slope Detector
The only advantages of the basic slope detector circuit is its simplicity.
To overcome the drawbacks of the simple slope detector, a Balanced slope detector is used.
 Balanced FM Slope Detector (Balanced
Frequency Discriminator)

• The input transformer has a center tapped

secondary. Hence, the input voltages to the
two slope detectors are 180° out of phase.
• There are three tuned circuits.
• Out of them, the primary is tuned to IF i.e., fc .
• The upper tuned circuit of the secondary (T1)
is tuned above fc by Δf i.e., its resonant
frequency is (fc+ Δf).
• The lower tuned circuit of the secondary is tuned below fc by Δf i.e., at (fc – Δf).
• R1C1 and R2C2 are the filters used to bypass the RF ripple.
• Vo1 and Vo2 are the output voltages of the two slope detectors.
• The final output voltage Vo is obtained by taking the subtraction of the individual
output voltages, Vo1 and Vo2, i.e.,
Working Operation of the Circuit
The circuit operation can be explained by dividing the input frequency into three ranges as
follows:

(i) fin = fc: When the input frequency is instantaneously equal to fc, the induced voltage in
the T1 winding of secondary is exactly equal to that induced in the winding T 2.

Thus, the input voltages to both the diodes D1 and D2 will be the same.

Therefore, their dc output voltages Vo1 and Vo2 will also be identical but they have opposite
polarities. Hence, the net output voltage Vo = 0.

(ii) fc < fin < (fc + Δf): In this range of input frequency, the induced voltage in the winding T 1 is
higher than that induced in T2.

Therefore, the input to D1 is higher than D2.

Hence, the positive output Vo1 of D1 is higher than the negative output Vo2 of D2.

Therefore, the output voltage Vo is positive.

As the input frequency increases towards (fc + Δf), the positive output voltage increases as
shown in 3.
Advantages
(i) This circuit is more efficient than simple slope detector.

(ii) It has better linearity than the simple slope detector.

Drawbacks
(i) Even though linearity is good, it is not good enough.

(ii) This circuit is difficult to tune since the three tuned circuits are to
be tuned at different frequencies i.e., fc, (fc+Δf) and (fc – Δf).

(iii) Amplitude limiting is not provided.

Foster Seeley Detector – Circuit Diagram, Working and its
Phasor Diagram:
The circuit diagram of the Foster Seeley detector is shown in Fig. 22.54. This Foster
Seeley Detector circuit consists of an inductively coupled double tuned circuit in which
both primary and secondary coils are tuned to the same frequency (intermediate
frequency).
The center of the secondary coil is connected to the top of the primary (collector end) through a
capacitor C. This capacitor C performs the following functions:
[Link] blocks the dc from primary to secondary.
[Link] couples the signal frequency from primary to center tapping of secondary.
The primary voltage V3 (i.e., the signal voltage) thus appears across the inductor L. Nearly entire
voltage V3 appears across inductor L except a small drop across the capacitor C. However, by a
suitable choice of C and L, the voltage drop across the capacitor C can be made negligible.
The centre tapping of the secondary coil has an equal and opposite voltage across each half
winding. Hence V1 and V2 are equal in magnitude but opposite in phase. The radio frequency
voltages Va1 and Va2 applied to the diodes D1 and D2 are expressed as
Voltage Va1 and Va2 depend upon the phase relations between V1, V2 and V3. The phasor diagrams of
Foster Seeley Detector for different frequencies have been shown in Fig. 22.55. The phasors V1 and V2 are
always equal in magnitude but in phase opposition. However, the phase position of V1 and V2 relative to V3
would depend upon the tuned secondary coil at the resonance or off the resonance as discussed below :

1. At Resonance: When an input voltage has a frequency equal to the resonant frequency fif of the tuned
secondary, V3 is in phase quadrature (90° out of phase) with V1 and V2. This has been indicated in Fig.
22.55 (a). The resultant voltages Va1 and Va2 are equal in magnitude.

2. Off Resonance: When the input voltage is off the resonant frequency fif of the tuned secondary, the
phase position of V1 and V2 relative to V3 will be different from 90°. Let Qs be the quality factor of tuned
secondary coil. When an input signal frequency exceeds the resonant frequency fif by an amount fif/2Qs
the phase difference between V3 and V1 is 45° as shown in Fig. 22.55 (b). Because V2 is in phase
opposition of V1, the phase difference between V3 and V2 is 135°. The phasor diagram shown in Fig. 22.55
(b) reveals that Va1 is reduced whereas Va2 is increased. The situation is reversed when the input voltage
has a frequency below fif which is evident from the phasor diagram shown in Fig. 22.55 (c). Thus the
magnitude of the voltages Va1 and Va2 will vary with the instantaneous frequency f in the manner shown
in Fig. 22.56.
The RF voltages Va1 and Va2 are separately rectified by the diodes D1 and D2
respectively to provide voltages Vout1 and Vout2. The RF components are bypassed
by the capacitors leaving only modulating frequency component and a dc term. The
voltages Vout1 and Vout2 then represent the amplitude variations of voltages Va1 and
Va2 respectively. The diodes are so arranged that the output voltage Vout is equal to
the arithmetic difference | Vout2 | – | Vout1 |.

Thus, the output voltage Vout will vary with instantaneous frequency in accordance
with the difference | Vout2 | – | Vout1 |, as shown by the dotted curve in Fig. 22.56
(b). This allotted curve is known as discriminator characteristic in Fig. 22.56.
Phase Locked Loop Working Principle:

A Phase Locked Loop Working is basically a closed loop system designed to lock the output
frequency and phase to the frequency and phase of an input signal. It is commonly
abbreviated as Basics of PLL.

The PLL was first introduced in its discrete form in early 1930s. The high cost of realizing Phase
Locked Loop Working in discrete form, limited its use earlier. Now with the advanced IC
technology, PLLs are available as inexpensive monolithic ICs. They are used in applications
such as frequency synthesis, frequency modulation/demodulation, AM detection, tracking
filters, FSK demodulator, tone detector etc.

The balanced modulator is an excellent building block for communication equipments. It can
be used as a amplitude modulator, product detector, amplitude demodulator, mixer, frequency
doubler, frequency detector and phase detector.
 PLL Block Diagram:

It consists of

•Phase detector

•Low pass filter

•Error amplifier

•Voltage Controlled Oscillator (VCO)

The phase detector compares the input frequency fi with the feedback frequency fo and
generates an output signal which is a function of the difference between the phases of the two
input signals. The output signal of the phase detector is a dc voltage. The output of phase
detector is applied to low-pass filter to remove high frequency noise from the dc voltage. The
output of low pass filter without high frequency noise is often referred to as error voltage or
control voltage for VCO.

When control voltage is zero, VCO is in free running mode and its output frequency is called as
centre frequency fo. The non-zero control voltage results in a shift in the VCO frequency from its
free-running frequency, fo to a frequency f, given by f = fo + KV VC
where KV is the voltage to frequency transfer coefficient of the VCO. The error or control
voltage applied as an input to the VCO, forces the VCO to change its output frequency in the
direction that reduces the difference between the input frequency and the output frequency
of VCO.

This action, commonly known as capturing, continues till the output frequency of VCO is
same as the input signal frequency. Once the two frequencies are same, the circuit is said to
be locked. In locked condition, phase detector generates a constant dc level which is required
to shift the output frequency of VCO from centre frequency to the input frequency. Once
locked, PLL tracks the frequency changes of the input signal. Thus, a Phase Locked Loop
Working goes through three states. : free running, capture and phase lock.
Lock Range:

When PLL is in lock, it can track frequency changes in the incoming signal. The range of
frequencies over which the PLL can maintain lock with the incoming signal is called the lock
range or tracking range of the PLL. It is usually expressed as a percentage of fo, the VCO
frequency.
Capture Range:

The range of frequencies over which the PLL can acquire lock with an input signal is called
the capture range. It is also expressed as a percentage of fo.

Pull In Time:

The capture of an input signal does not take place as soon as the signal is applied, but it
takes finite time. The total time taken by the PLL to establish lock is called pull in
time. This depends on the initial phase and frequency difference between the two signals
as well as on the overall loop again and the bandwidth or the low pass filter.