8086 Interrupt

Structure:
Hardware software and program generated interrupts in 8086.
Response to interrupt, Interrupt vector Table, Interrupt acknowledge
machine cycle, 8259 PCI, EOI, and interfacing with 8086.
 8086 Interrupts
• Interrupt is the method of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor.

• Whenever an interrupt occurs, the processor completes the current instruction and starts
the implementation of an Interrupt Service Routine (ISR) or Interrupt Handler.

• ISR is a program that tells the processor what to do when the interrupt occurs.

• After the ISR execution, control returns to the main routine where it was interrupted
 Steps in executing an interrupt

• In the 8086 microprocessor following tasks are performed when the microprocessor
encounters an interrupt:
• The value of the flag register is pushed into the stack.

• The value of starting memory address of CS (Code Segment) is pushed into the stack.

• The value of IP (Instruction Pointer) is pushed into the stack.

• IP is loaded from word location (Interrupt type) * 04..

• CS is loaded from the following word location.

• Interrupt, and Trap flags are reset to 0.

Types of Interrupt
Interrupt Types
in 8086

Software Hardware
Interrupt Interrupt

256 types of
Software non-maskable interrupt
Interrupt

maskable interrupt request

 NMI (non-maskable interrupt)
• Having higher priority than INTR.

• Type 2 interrupt

• When this interrupt is activated, following actions take place −

• Completes the current instruction that is in progress.
• Pushes the Flag register values on to the stack.
• Pushes the CS (code segment) value and IP (instruction pointer) value of the return
address on to the stack.
• IP is loaded from the contents of the word location 00008H(Type 2*4=00008 H).
• CS is loaded from the contents of the next word location 0000AH.
• Interrupt flag and trap flag are reset to 0.
 Hardware Interrupts
• Hardware interrupt is caused by any peripheral device by sending a signal
through a specified pin to the microprocessor.

• The 8086 has two hardware interrupt pins,

1. NMI (non-maskable interrupt)--- Higher Priority
2. INTR (maskable interrupt request) --- Lower Priority
Need of NMI
• Used during power failure

• Used during critical response time

• Used during non-recoverable hardware errors

 INTR

• The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled using
set interrupt flag instruction.

• It is a level-triggered interrupt.

• This interrupt can be masked or delayed.

• The INTR interrupt is activated by an I/O port.

• If the interrupt is enabled and NMI is disabled, then the microprocessor first completes the current execution and
sends ‘0’ on INTA pin twice.

• The first ‘0’ means INTA informs the external device to get ready and during the second ‘0’ the microprocessor
receives the 8 bit from PIC (Type of Interrupt) .
Interrupt Acknowledge Machine
Cycle
 INTR
• When this interrupt is activated, following actions take place −
• First completes the current instruction.

• Activates INTA output and receives the interrupt type, say X.

• Flag register value, CS value of the return address and IP value of the return address are
pushed on to the stack.

• IP value is loaded from the contents of word location X × 4

• CS is loaded from the contents of the next word location.

• Interrupt flag and trap flag is reset to 0

 Software Interrupts
• These are instructions inserted within the program to generate interrupts.

• There are 256 software interrupts in the 8086 microprocessor.

• Interrupts are generated by a software instruction and operate similarly to a jump or branch
instruction.

• The instructions are of the format INT type, where the type ranges from 00 to FF.

• The starting address ranges from 00000 H to 003FF H.

• These are 2-byte instructions.

• IP is loaded from type * 04 H, and CS is loaded from the following address given by (type * 04) + 02 H.
 Interrupts are divided into three groups

• Type 0 to Type4 (Dedicated Interrupts)

• TYPE 0 corresponds to division by zero(0).
• TYPE 1 is used for single-step execution for debugging the program.
• TYPE 2 represents NMI and is used in power failure conditions.
• TYPE 3 represents a break-point interrupt.
• TYPE 4 is the overflow interrupt.

• Type 5 to 31(Not used by 8086, reserved for higher processor like 80286,80386….

• Type 32-255(Available for user)

 Interrupt Vector Table
• For every interrupt, there is a fixed location in memory that holds the address of its interrupt
service routine(ISR).

• The group of memory locations set aside to hold the addresses of ISRs is called the interrupt
vector table.

• When an interrupt is occurred, the microprocessor stops execution of current instruction.

• It transfers the content of program counter (CS and IP) into stack.

• After this, it jumps to the memory location specified by Interrupt Vector Table (IVT).

• After that the code written on that memory area will execute.
Interrupt Vector Table
Programmable Interrupt
Controller 8259
 8259 PIC Microcontroller
• There are 2 hardware interrupts in Intel 8086 microprocessors respectively.

• But by connecting Intel 8259 with these microprocessors, we can increase their interrupt
handling capability.

• Intel 8259 combines the multi-interrupt input sources into a single interrupt output.

• Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7.

Block Diagram of 8259

Block Diagram consists of 8 blocks

which are –
• Data Bus Buffer,
• Read/Write Logic,
• Cascade Buffer Comparator,
• Control Logic,
• Priority Resolver
• 3 registers- ISR, IRR, IMR.
Data bus buffer –

• Mediator between 8259 and 8086 microprocessor by acting as a buffer.

• Takes the control word from microprocessor and transfer it to the control logic of 8259
microprocessor.

• After selection of Interrupt by 8259 microprocessor (based on priority of the interrupt), it transfer
the opcode of the selected Interrupt and address of the Interrupt service sub routine to the other
connected microprocessor.

• The data bus buffer consists of 8 bits represented as D0-D7 in the block diagram.

Read/Write logic –

• This block works only when the value of pin CS is low (as this pin is active low).

• responsible for the flow of data depending upon the inputs of RD and WR.
Interrupt request register (IRR):
• IRR stores all the interrupt inputs that are requesting service.

• It keeps track of which interrupt inputs are asking for service.

• If an interrupt input is enabled, and has an interrupt signal on it, then the corresponding bit in the IRR will be set.

• The IRR is used to indicate all the interrupt levels which are requesting service,

In service register (ISR):

• ISR is used to store all the interrupt levels which are currently being serviced.

• The in service registers keeps tracks of which interrupt inputs are currently being serviced.

• For each input that is currently being serviced the corresponding bit will be set in the in service register.
8259 PIC