Chapter 7
The Design of Sequential Systems
Outlines
• Introduction
• Flip Flop Design Techniques
• The Design of Synchronous Counters
• Design of Asynchronous Counters
Introduction
• Design procedure of sequential logic
– Design specification (described by natural
languages)
– Formalize the design specification by state diagram
– State reduction
– State assignment
– Derive next state and output equations and simplify
those Boolean functions
– Implement the simplified Boolean functions with
the available logic gates and flip-flops
Flip Flop Design Techniques
• Design example
– System modeling: State diagram and state table
Flip Flop Design Techniques
– State assignments
Flip Flop Design Techniques
– Design truth table (choice (a) state assignment)
Next state table
Output table
Flip Flop Design Techniques
– Simplification of next state and output functions
Flip Flop Design Techniques
– Implementation using D flip-flops
Flip Flop Design Techniques
• Repeat the process for the JK flip-flops
– Design truth table (choice (a) state assignment
and apply the excitation table of JK flip-flop)
Next state and input function table
Excitation table of
JK flip-flop
Flip Flop Design Techniques
– Simplification of input functions
Flip Flop Design Techniques
• Repeat the process for the SR flip-flops
– Design truth table (choice (a) state assignment
and apply the excitation table of SR flip-flop)
Next state and input function table
Excitation table of
SR flip-flop
Flip Flop Design Techniques
– Simplification of input functions
Flip Flop Design Techniques
• Repeat the process for the SR flip-flops
– Design truth table (choice (a) state assignment
and apply the excitation table of T flip-flop)
Next state and input function table
Excitation table of
T flip-flop
Flip Flop Design Techniques
– Simplification of input functions
The Design of Synchronous Counters
• Counter
– With no data input
– Go through a fixed sequence of states on
successive clocks
– The output is just the state of the system—the
contents of all of the flip flops
The Design of Synchronous Counters
• MOD-16 counter
The Design of Synchronous Counters
• D flip flops for MOD-16 counter
DD DC ' DB ' DA' D' CBA
DC CB 'CA'C ' BA
DB B ' A BA'
DA A'
The Design of Synchronous Counters
• JK flip-flops for MOD-16 counter
– Applying the characteristic equations to design
Qn 1 JQn' K ' Qn
Dn 1 DC ' DB ' DA' D' CBA Cn 1 CB 'CA'C ' BA
(CBA) D'(C ' B ' A' ) D ( BA)C '( B' A' )C
(CBA) D'(CBA)' D ( BA)C '( BA)' C
' '
Dn 1 J D D K D Cn 1 J C C ' K C' C
D
J D CBA J C BA
K D CBA K C BA
The Design of Synchronous Counters
Bn 1 B ' A BA' An 1 A'
( A) B '( A)' B (1) A'(1)' A
'
Bn 1 J B B K B ' An 1 J A A' K A' A
B
J B A J A 1
KB A K A 1
The Design of Synchronous Counters
– MOD-16 circuit using JK flip flops
1
A
BA
CBA
Carry
The Design of Synchronous Counters
• Up/Down counter—MOD-8
x=0
Up count
x=1
Down count
The Design of Synchronous Counters
Cn 1 x' C ' BA xC ' B' A' x' CB ' xCA CBA'
Bn 1 xB' A' x' B' A xBA x' BA'
An 1 A'
The Design of Synchronous Counters
• JK flip-flops for MOD-16 counter
– Applying the characteristic equations to design
Cn 1 x' C ' BA xC ' B ' A' x' CB ' xCA CBA'
( x' BA xB ' A' )C '( x' B' xA BA' )C
J C x' BA xB ' A'
K C ( x' B' xA BA' )' ( x B)( x' A' )( B' A)
( xA' x' B BA' )( B ' A)
xB ' A'0 0 0 x' BA 0
xB ' A' x' BA
The Design of Synchronous Counters
Bn 1 xB' A' x' B' A xBA x' BA'
( xA' x' A) B'( xA x' A' ) B
J B xA' x' A
K B ( xA x' A' )' xA' x' A
An 1 A'
1 A'1' A
J A 1
K A 1
The Design of Synchronous Counters
– Up/Down counter circuit using JK flip flops
The Design of Synchronous Counters
• MOD-10 counter
The Design of Synchronous Counters
Dn 1 D' CBA DA' Cn 1 C ' BA CB 'CA' Bn 1 D' B' A BA'
(CBA) D'( A)' D ( BA)C '( BA)' C ( D' A) B'( A)' B
J D CBA J C K D BA J B D ' A
KD A K A An 1 A'
B
1 A'(1)' A
J A K A 1
The Design of Synchronous Counters
• Example: MOD-7 counter
The Design of Synchronous Counters
• Using D, JK flip flops
D3,n 1 q2'
D1,n 1 q2' q3 q2 q3' D2,n 1 q1' q2' q3' q1 q2' q3 q1' q2 q3
or
D1,n 1 q1' q2' q3 q1' q2 q3' q1 q2' q3
The Design of Synchronous Counters
D1,n 1 q1' q2' q3 q1' q2 q3' q1 q2' q3 D2,n 1 q1' q2' q3' q1 q2' q3 q1' q2 q3
q2' q3 q2 q3' q1' q2' q3 q1 q1' q3' q1 q3 q2' q1' q3 q2
J1 q2' q3 q2 q3' J 2 q1' q3' q1 q3
K1 q2' q3 ' q2 q3' K 2 q1' q3 ' q1 q3'
D3,n 1 q2' (q3' q3 ) (q2' )q3' (q2 )' q3'
J 3 q2'
K 3 q2
The Design of Synchronous Counters
– Function analysis
The Design of Synchronous Counters
– Using SR, T flip flops
The Design of Synchronous Counters
The Design of Synchronous Counters
The Design of Asynchronous Counters
• Designed without a clock input
The Design of Asynchronous Counters
• A 4-bit asynchronous counter
The Design of Asynchronous Counters
• Design an asynchronous MOD-12 counter
using JK flip-flop
The Design of Asynchronous Counters