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RTL Design Example: Differential Solver

The document presents a detailed example of designing a 2nd order differential equation solver using RTL (Register Transfer Level) design methodology. It includes preprocessing steps, scheduling, register allocation, functional unit allocation, and controller synthesis, culminating in the final RTL behavior and control signals. The example illustrates the transformation of a mathematical algorithm into a hardware description suitable for implementation.

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18 views17 pages

RTL Design Example: Differential Solver

The document presents a detailed example of designing a 2nd order differential equation solver using RTL (Register Transfer Level) design methodology. It includes preprocessing steps, scheduling, register allocation, functional unit allocation, and controller synthesis, culminating in the final RTL behavior and control signals. The example illustrates the transformation of a mathematical algorithm into a hardware description suitable for implementation.

Uploaded by

saiswapnith2
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

RTL Design Example

Working with an example

Example: 2nd order differential equation solver


Diffeq: (x, dx, u, a, clock, y)
input: x, dx, u, a, clock;
output: y
while(x < a)
u1 = u-(3*x*u*dx)-(3*y*dx);
CDFG
y1 = y+(u*dx);
x1 = x+dx;
x = x1, y = y1, u = u1;
end
Preprocessing Example: 2nd order differential equation solver
Diffeq: (x, dx, u, a, clock, y)
input: x, dx, u, a, clock;
output: y
while(x < a)
I B1
u1 = u-(3*x*u*dx)-(3*y*dx);
V1 : t1 = u * dx
Read(p1, dx) y1 = y+(u*dx);
V2 : t2 = 3 * x x1 = x+dx;
Read(p2, x)
V3 : t3 = 3 * y x = x1, y = y1, u = u1;
Read(p3, a) V4 : t4 = u * dx end

Read(p1,y) V5 : t5 = t1 * t2
Read(p2, u) V6 : t6 = t3 * dx
V7 : t7 = u – t5
c=x<a
V8 : u = t7 – t6
V9 : y = y + t4
V10 : x = x + dx
B2 V11 : c = x < a
Write(p1, y)
Basic Blocks with 3-address codes Control and Dataflow graph (CDFG)
Preprocessing
B1
V1 : t1 = u * dx
V2 : t2 = 3 * x
V3 : t3 = 3 * y
V4 : t4 = u * dx
V5 : t5 = t1 * t2
V6 : t6 = t3 * dx
V7 : t7 = u – t5
V8 : u = t7 – t6
V9 : y = y + t4
V10 : x = x + dx
V11 : c = x < a
Preprocessing
u dx 3 x y dx
B1
V1 : t1 = u * dx
V4
V2 : t2 = 3 * x V1 * t1 * V2 * V10 + t8
V3 : t3 = 3 * y t2 t4

V4 : t4 = u * dx
V5 * t5 V 3 * t3 V9 +
V5 : t5 = t1 * t2
V6 : t6 = t3 * dx
V7 : t7 = u – t5 V7 - t7 V6 * t 6 V11 a<
V8 : u = t7 – t6
V9 : y = y + t4
V8 - c
V10 : x = x + dx
V11 : c = x < a
Date dependency graph
IIT Guwahati 5
Scheduling
u dx 3 x y dx

V4
S1 V1 * t 1 * V2 * V10 + t8
t2 t4

S2 V5 * t 5 V3 * t 3 V9 +

I
S3 V7 - t 7 V6 * t 6 V11 <

S4 V8 - c

IIT Guwahati 6
R1: t1, t3, t6
Register Allocation and Binding R : t2, t5, t7
Var S1 S2 S3 S4 2

t1
R1 R3: t4
u dx 3 x y dx R2
t2
R1
R4: t8
t3

S1 V1 * t1 * V2
V4
* V10 + t8
t4 R3
R2
R5: u
t5
t4
t2 t6
R1
R6: x
R2
t7
S2 V5 * t5 V3 * t3 V9 + t8 R4 R7: dx
u R5

I x R6 R8: y
S3 V7 - t7 V6 * t6 V11 < R7
dx

y R8
R9: c
S4 V8 - c
c
R9

R10
R10: 3
3
a
R11
R11: a
IIT Guwahati Interval graph 7
FU Allocation and Binding: Multiplier
S1 S2 S3 S4
u dx 3 x y dx
M1
V1
V4 M2
S1 V1 * t1 * V2 * V10 + t8 V2
t2 t4
M2
V3
S2 V5 * t5 V3 * t3 V9 +
M3
V4
I M1
S3 V7 - t7 V6 * t6 V11 < V5
M3
V6
S4 V8 - c

MULT: M1: V1, V5


Mult operations with non-overlapping schedule MULT: M2: V2, V3
can be mapped to the same Multiplier FU
MULT: M3: V4, V6
IIT Guwahati 8
FU Allocation and Binding: Adder
u dx 3 x y dx

Var S1 S2 S3 S4
V4
S1 V1 * t1 * V2 * V10 + t8
t2 t4 A1
V10
S2 V5 * t5 V3 * t3 V9 +
A1
V9
A1
I
S3 V7 - t7 V6 * t6 V11 <
V7
A1
V8
S4 V8 - c

FU allocation and Binding


Add/Sub operations with non-overlapping A1: v10, v9, v7, v6
schedule can be mapped to the same adder FU
IIT Guwahati 9
Functional Unit Allocation and
Binding
FU alloc and bind:
MULT: M1: V1, V5
MULT: M2: V2, V3
MULT: M3: V4, V6
ADD: A1: V7, V8, V9, V10
COMP: C1: V11

IIT Guwahati 10
Register Transfer Level (RTL) Behaviour
R1: t 1, t 3, t 6
S1: S1:
R2: t 2, t 5, t 7 FU alloc and bind:
V1 : t1 = u * dx R3: t4
V1 R1 = R5 <M1> R7
MULT: M1: V1, V5
V2 : t 2 = 3 * x R4: t8 V2 R2 = R10 <M2> R6
MULT: M1: V2, V3
V4 : t4 = u * dx R5: u V4 R3 = R5 <M3> R7
MULT: M1: V4, V6
V10 : x = x + dx R6: x
ADD: A1: V7, V8, V9, V10 V10 R4 = R6 <A> R7
R7: dx
COMP: C1: V11
S2: R8: y S2:
R9: c FU mapping
V5 : t 5 = t 1 * t 2 V5 R2 = R1 <M1> R2
R10: 3
V3 : t 3 = 3 * y V3 R1 = R10 <M2> R8
R11: a
V9 : ybehaviour
Original = y + t4 V9 R8 = R8 <A> R3
Register mapping
RTL behaviour

IIT Guwahati 11
Datapath Synthesis
R1, R2, R1, R5, R4 R6, R1, R5, R6, R2

FU

R1, R1, R2, R7, R4

IIT Guwahati 12
Data path Synthesis
S1:
V1 R1 = R5 <M1> R7
V2 R2 = R10 <M2> R6
V4 R3 = R5 <M3> R7
V10 R4 = R6 <A> R7

S2:
V5 R2 = R1 <M1> R2
V3 R1 = R10 <M2> R8
V9 R8 = R8 <A> R3

IIT Guwahati 13
Data path Generation

IIT Guwahati 14
Controller Synthesis
REGISTERS
a
3
d
x enable
y
u
r
+917075752330 1r
2
Mux control

ALU control (+,-,<)


AL
*

c
U

DATA-PATH CONTROL-UNIT
IIT Guwahati 15
Final RTL

<1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 0, 0, 1>

IIT Guwahati 16
Control Signals

Control Assertion Pattern: <FU, FU_MUX_in, Reg-en, Reg_Mux_in>


FU: 1 bit
S1 :
FU_MUX_in: 7 bits
V1 R1 = R5 <M1> R7
Reg_en: 11 bits
V2 R2 = R10 <M2> R6
Reg_MUX_in: 2 bits
V4 R3 = R5 <M3> R7
Total: 21 bits
V10 R4 = R6 <A> R7
S1: <1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 0, 0, 1>
S2: <1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0 0, 1, 0> S2 :
S3: <…..> V5 R2 = R1 <M1> R2
S4: <…..> V3 R1 = R10 <M2> R8
IIT Guwahati
V9 R8 = R8 <A> R3 17

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