Clock System Architecture
• Figure 13.21 shows an overview of a
typical clock subsystem.
• The chip receives an external clock
signal through the I/O pads.
• The clock generation unit may include
a phase-locked loop (PLL) or delay-
locked loop (DLL) to adjust the
frequency or phase of the global clock. • The clock distribution network must be
carefully designed to minimize clock
• This global clock is then distributed skew.
across the chip to points near all of the • Local clock gaters receive this global
clocked elements. clock and drive the physical clock signals
along short wires to small groups of
clocked elements
Global Clock Generation
• The global clock generator receives an
external clock signal and produces the
global clock that will be distributed
across the die.
• More sophisticated clock generators use
either phase-locked loops (PLLs) or
delay-locked loops (DLLs) to regulate
the delay to a constant value in the
presence of variation and noise.
Global Clock Generation
• Figure 13.22 illustrates the use of a PLL or a DLL to compensate for the on-chip clock
delays.
• The circuits contain a phase detector (PD) that produces a signal proportional to the phase
difference between the input and output clocks.
• The loop filter (LF) converts this phase error into a control signal adjusting the frequency
of an oscillator or the delay of a delay line.
• The output is then buffered to drive the large output clock load.
• PLLs and DLLs share the same principle of feedback control; they both monitor the
distributed clocks and correct them if they are in misalignment with the external input
clock.
• The only difference is that upon the detection of misalignment, a PLL adjusts the
frequency of the clock (subsequently its phase) while a DLL adjusts the delay of the
clock. Nonetheless, both types of feedback loops strive to distribute the clocks whose edge
positions are aligned with those of the external clock.
Local clock gaters
• Local clock gaters receive the global clock and produce the physical clocks
required by the clocked elements.
• The output of the gaters typically run a short distance (< 1 mm) to the clocked
elements.
• Clock gaters are often used to stop or gate the clock to unused blocks of logic to
save power.
• They can produce a variety of modified clock waveforms including pulsed clocks,
delayed clocks, stretched clocks, nonoverlapping clocks, and double-frequency
pulsed clocks.
• When used to modify the clock edges, they are sometimes called clock choppers
or clock stretchers. Figure 13.29 shows a variety of clock gaters.
Local clock gaters
Global Clock Distribution
• The global clock must be distributed across the chip in a way that reaches all of the
clocked elements at nearly the same time. In antiquated processes with slow transistors and
fast wires, the clock wire had negligible delay and any convenient routing plan could be
used to distribute the clock.
• Clock distribution system must be carefully designed to equalize the flight time between
the clock generator and the clocked receivers.
• Global clock distribution networks can be classified as
• grids,
• H-trees,
• spines,
• ad hoc, or
• hybrid
Grids
Alpha 21064 Alpha 21164 Alpha 21264
• A clock grid is a mesh of horizontal and
vertical wires driven from the middle or
edges.
• The mesh is fine enough to deliver the clock
to points nearby every clocked element. PLL
• The resistance is low between any two
nearby points in the mesh so the skew is gclk grid gclk grid
also low between nearby clocked elements.
• This reduces the chance of hold-time
problems because such problems tend to
occur between nearby elements where the
propagation delay between elements is also Alpha 21064 Alpha 21164 Alpha 21264
small.
Grids
• Grids also compensate for much of the random skew because shorting the
clock together makes variations in delays irrelevant.
• The grids can be routed early in the design without detailed knowledge of
latch placement.
• However, grids do have significant systematic skew between the points closest
to the drivers and the points farthest away.
• They also consume a large amount of metal resources and hence have a high
switching capacitance and power consumption.
H-tree
• An H-tree is a fractal structure built by drawing an
H shape, then recursively drawing H shapes on each
of the vertices, as shown in Figure 13.24. A B
• With enough recursions, the H-tree can distribute a
clock from the center to within an arbitrarily
short distance of every point on the chip while
maintaining exactly equal wire lengths.
• Buffers are added as necessary to serve as repeaters.
If the clock loads were uniformly distributed around
the chip, the H-tree would have zero systematic skew.
• Moreover, the trees tend to use less wire and thus FIGURE 13.24 H-tree
have lower capacitance than grids
H-tree
• In practice, the H-tree still shows some skew because the clock loads are not
uniform, loading some leaves of the tree more than others. Moreover, the tree
often must be routed around obstructions such as memory arrays. The leaves of
the H do not reach every point on the chip, so some short physical clock wires
are required after the local clock gater.
• Nevertheless, with careful tapering of the wires and sizing of the clock gaters, H-
trees can deliver nearly zero systematic skew.
• A drawback of H-trees is that they may have high random skew, drift, and
jitter between two nearby points that are leaves of different legs of the tree.
For example, the points A and B in Figure 13.24 might experience large skews. As
the points are close, this is a particular problem for hold times .
Hybrid
• A hybrid combination of the H-tree and grid clock distribution scheme
• It offers lower skew than either an H-tree or grid alone.
• In the hybrid approach, an H-tree is used to distribute the clock to a large number of
points across the die. A grid shorts these points together.
• Compared to a simple grid, the hybrid approach has lower systematic skew because the
grid is driven from many points instead of just the middle or edge.
• Compared to an H-tree, the hybrid approach is less susceptible to skew from
nonuniform load distributions.
• The grid also reduces local skew and brings the clock near every location where it is
needed.
• Finally, the hybrid approach is regular, making layout of well-controlled transmission
line structures easier.
Spines
• Figure 13.27 shows a clock distribution
scheme using a pair of spines.
• As with the grid, the clock buffers are
located in a few rows across the chip.
• However, instead of driving a single clock
grid across the entire die, the spines drive
length-matched serpentine wires to each
small group of clocked elements.
• If the loads are uniform, the spine avoids the
systematic skew of the grid by matching the
length of the clock wires.
Spines
• If the loads are uniform, the spine avoids the systematic skew of the grid by
matching the length of the clock wires.
• Each serpentine is driven individually so gaters can be used to save power by not
switching certain wires.
• The serpentine is also easy to design and each load can be tuned individually.
• However, a system with many clocked elements may require a large number of
serpentine routes, leading to high area and capacitance for the clock network.
• Like trees, spines also may have large local skews between nearby elements
driven by different serpentines.
Spines
The Pentium II and III use a pair of
clock spines. The Pentium 4 adds a
third clock spine to reduce the length
of the final clock wires.
Figure 13.28(a) shows the global
clock buffers distributing the clock to
the three spines on the Pentium 4 with
zero systematic skew while Figure
13.28(b) shows a photograph of the
chip annotated with the clock spine
locations
Adaptive Deskewing
• Additional adjustable delay buffers can be
used to compensate for mismatches in clock
distribution delay along various paths.
• For example, the Pentium II and 4 use such
buffers at the leaves of the clock spine to
eliminate systematic and random variations
in the clock distribution network.
• Figure 13.32 shows an example of a
digitally adjustable delay line with eight
levels of adjustment.
• The select signals use a thermometer code This technique is sometimes called adaptive
to produce a monotonically decreasing deskewing
propagation delay as more pass transistors
are turned on.