DDR4/5 SUBSYSTEM

VERIFICATION
Block diagram
Description
 In DDRSS contains 2 DDR controllers,1 MCI block, DDRPHY, CSR and PLL block
 DDR memory device(VIP)
 Two AXI interfaces and 3 APB interfaces are there.
 AXI initiates the read/write transactions to the controller.
 APB is used to configure the registers.
 Controller sends the command to DDRPHY through DFI.
 DDRPHY is used to convert the DFI address into memory address.
 MCI block is used to select anyone of the channel coming from DDR controllers. it acts as an arbiter.
 PLL block used to generate the required clock frequency to the DDR controllers and DDRPHY.
 CSR block is used to configure the PLL registers.
 SMBUS is used to configure the RCD registers in DDR DIMM.
 We use AXI VIP, APB VIP, Memory Model VIP from cadence.
Objective

 Main Aim of this project is to verify the functional features and performance validation of DDR4/5
subsystem level
 DDR SS SUPPORTED FEATURES
 DDR subsystem supports 1. DDR4 Device(X4/X8)
2. DDR5 Device (X4/X8)
3. DDR4 DIMM
4. DDR5 DIMM
 Performance:
 AXI features supported.
 Frequency ratios supported(1:2/1:4)
 Address mapping techniques
 Address boundary
 BIST
 Low power mode scenarios

 RAS Features:
 ECC
 Scrubbing features
 CA parity

DDR4 FEATURES
 VDD=VDDQ = 1.2v, Vpp=2.5  MPR Read & write capability
 On-die, internal, adjustable VREFDQ generation  Write levelling
 1.2V pseudo Open drain i/o  Self Refresh mode
 TC max up to 95°C  Low power Auto self Refresh
 64ms, 8192-cycle refresh up to 85 c  Temp Controlled refresh
 32ms, 8192 - cycle refresh at>85 to 95c  FINE granularity refresh
 16 internal banks (x4, X8): 4groups of 4banks each  Self refresh abort
 8 internal banks (x16): 2 groups of 4banks each
 max power saving
 8n bit prefetch Architecture
 O/p driver Calibration
 programmable data strobe preambles
 nominal, park, and dynamic on-die termination
 Data Strobe preamble –training
 DBI for data bus
 Cmd/Address Latency (CAL)
 CMD & Address (CA) parity
 Per DRAM addressability
 Data bus write cyclic redundancy check (CRC)
 DDR5 FEATURES
 CS/CA training mode
 VDD=VDDQ=1.1v Vpp=1.8v
 On-die ECC
 On-die, internal, adjustable VREF generation for DQ, CA,CS
 ECC-transparency and error scrub
 1.1v pseudo open-drain I/O
 Decision feedback equalization
 TC max up to 95°c
 Loopback mode
 32ms, 8192 cycle refresh up to 85°C
 SPPR and HPPR capability
 16ms, 8192 Cycle refresh At>85°C to 95°c
 write/read cycle redundancy check (CRC)
 32 internal banks(X4,x8): 8 groups of 4banks each
 Per-DRAM addressability
 16 internal banks (x16): 4 groups of 4banks each
 DQ VREF –training
 16n prefetch architecture
 Duty cycle adjuster
 1cycle 2 cycle Cmd Structure
 mode Register Read/write
 2N mode
 Write levelling-training
 All bank and same bank refresh
 Programmable Preamble/ postamblе
 Multi purpose command
 Data mask
 Same bank pre charge
 Refresh management
 Max power saving mode
DDR5 UPDATES
MEMORY MODEL

In our verification 2 subsystems are there.

Each subsystem contains one physical channel supporting 2 ranks.
Each rank contains 10 chips, Out of those 8 are data chips and 2 are ECC chips

RANK0

ECC Data Data ECC

Fig: DIMM Inside Structure Fig: Dual channel DIMM
 DDR5 DIMM DEVICE
 Memory device contains 2 ranks per each channel.
 DDR device supports 1Tb(2^40 bit), for 2 channels 80 bits of data width(72(64+8(DM/DBI) bit data+8(ECC)).
 For X4 device = 80/4=20 devices
 Out of 20 devices, [0:7]=data from axi0(controller 0)
[8:9]= ECC DATA OF AXI0
[10:17]= data from axi1(controller 1)
[18:19]= ECC DATA OF AXI1
 For X8 device = 80/8=10 devices
 Out of 10 devices, [0:3]=data from axi0(controller 0)
[4]= ECC DATA OF AXI0
[5:8]= data from axi1(controller 1)
[9]= ECC DATA OF AXI1
 For X16 device = 80/16= 5 devices (Not applicable in this project)
 Out of 5 devices, [0:1]=data from axi0(controller 0)
[2]= ECC DATA OF AXI0
[3:4]= data from axi1(controller 1)
[2]= ECC DATA OF AXI1
CONVERSION(AXI TO DDR)
 Where incoming AXI address is divided into the ROW-COLUMN-BANK-BANKGROUP-CHIPSELECT
format depending on the type of memory used
 Memory controller converts incoming AXI logical address to the Device physical address depending upon
parameters configured MC like programmable_address_order.
 Minimum number of bits required to represent the row, column, bank, bankgroup is depends on type of
memory (X4, X8, X16) devices used and configuration setting. Number of bits can be vary depends on the
configuration
 The simplest address conversion is the mapping of MSB bits of AXI Address to the ROWs and LSB bits of
Address mapping to the Columns
AXI FEATURES

Axi- test plan : E:\chipsolve\chip solve\AXI\axi_noctestplan.xlsx

Why AXI?
 AXI is a high-performance, high-frequency protocol designed for efficient communication between
components in a system-on-chip (SoC) design.
 Separate address/control and data phases
 Support for unaligned data transfers, using byte strobes
 Uses burst-based transactions with only the start address issued
 Separate read and write data channels, that can provide low-cost Direct Memory Access (DMA)
 Support for issuing multiple outstanding addresses
 Support for out-of-order transaction completion
FREQUENCY RATIOS SUPPORTED FOR DDR4/5
 DDR4 supports 1:2 ratio
 DDR5 supports 1:2,1:4 ratio
 2/4 means DDRPHY to DDR device frequency(mem_clock) i.e 2400Mhz.
 1 indicates I/O clock frequency of controller to PHY. i,e=600mhz
 1:2 means 1200Mhz:2400Mhz (DDR5)
 1:4 means 600Mhz:2400Mhz(DDR5)
 1:2 means 800Mhz:1600Mhz (DDR4)
 DDR 4 supports 1.6Ghz frequency and DDR5 supports 2.4Ghz frequency.
 Data rate up to maximum of 3.2Gbps(DDR4) and 4.8Gbps(DDR5).
 ADDRESS MAPPING TECHNIQUES
 Axi_addr=f4_567f_f180
 Final address={cs_val_lower_axi_aadr[42:27], cs_vsl_upper_axi_addr[26:0]}
4 4 4 3 3 3 3 3 3 3 3 33 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
2 1 0 9 8 7 6 5 4 3 2 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

 Datapath=final_addr[1:0]
 Burstlength=final_addr[5:2]
 Bankgroup= final_addr[15], final_addr[7:6]}
 Coloumn= final_addr[14:8]
 bank= final_addr[17:16]
 Row= final_addr[34:18]
 Chipselect= final_addr[38:35]
 [39] bit refers to select the subsystem , value[0] =memory subsystem 0 and value[1] = memory subsystem 1
 Virtual pins[40:42]
CS CALCULATION
BIST(BUILT IN SELF TEST)
 BIST, is a testing mechanism integrated into devices like DDR5 memory to ensure they are functioning
correctly without the need for external testing equipment. DDR5 is the latest generation of DRAM,
offering higher performance and capacity compared to its predecessors.
 Here's how BIST is applied to DDR5:

[Link]-Test Capabilities:
DDR5 modules come with built-in circuitry that allows them to test their own memory cells and other
components. This helps in identifying faults or errors during the manufacturing process or in the field.
[Link] Testing:
BIST enables automated testing of DDR5 modules, which reduces the need for manual intervention and
speeds up the testing process.
[Link] Detection and Correction:
BIST in DDR5 can identify various types of errors, such as stuck-at faults, bridging faults, and more. It can
also assist in error correction by identifying defective areas that can be bypassed or corrected using error-
correcting code (ECC) mechanisms.
[Link]-Field Testing:
BIST allows for in-field testing of DDR5 modules, ensuring they continue to operate correctly over time. This
is useful for applications where high reliability is crucial, such as in data centers and enterprise systems.
[Link] Reliability:
BIST enhances the reliability of DDR5 modules by ensuring that only fully functional units are shipped to
customers. It also allows for periodic testing and maintenance, which can extend the lifespan of the memory
Modules.
Overall, BIST is a valuable feature for DDR5 memory, providing benefits in terms of quality control, cost
efficiency, and reliability.
 Low power mode scenarios

 When there are no memory accesses for a defined period, the system can enter Power-Down Mode to save
power.
 In this mode, the memory clock is disabled or reduced in frequency.
 Data retention is maintained, but power consumption is significantly reduced.
 There are two types: Active Power-Down (APD) and Precharge Power-Down (PPD).
 Reduces power usage when memory is idle.
 Auto refresh, Controller gives a command to DDR memory to get into Low power mode using DFI interface.
 self refresh, There is no inputs coming from controller to DDR memory, at that time DDR memory enters into
self refresh and then it goes to low power mode.
 In both cases power is saved.
 Example commands are given below
 dfi_lp_state: this signal indicates PHY to make memory device go to low power state
 dfi_lp_ip_wake: this signal indicates memory controller to PHY via the DFI interface and then wake up the
DDR device
Active Power-Down:

 Reduce Power Consumption:

Active Power Down helps in reducing the power consumption of the DDR5 memory during periods when full operation
is not required, without losing data integrity or needing a complete reset.

 Energy Efficiency:

It is aimed at enhancing the energy efficiency of the memory system, thus extending battery life in portable devices.

Pre-charge Power-Down:

 Pre-charge Command:
Before entering the power-down state, a pre-charge command is issued to close all open memory banks. This ensures that
all data is safely stored, and the memory is in a known state.

 Power Down Command:

After the pre charge command, a power-down command is issued to transition the memory into the low-power state.
DFS(Dynamic Frequency Scaling)

DFS (Dynamic Frequency Scaling) is a feature in DDR memory technologies that allows the memory controller to
dynamically adjust the frequency of the memory to optimize performance and power consumption based on current
system requirements.

Working of DFS

Initial Configuration:
 During system initialization, the memory controller sets the initial operating frequency of the DDR memory.
 This frequency is based on the system's performance requirements and the capabilities of the memory modules.

Monitoring Workload:
 The memory controller continuously monitors the system workload. It gathers information about memory usage,
data transfer rates, and other performance metrics to determine the current demand on the memory system.
Adjusting Frequency:

 Based on the workload analysis, the memory controller can decide to adjust the frequency. If the system
workload is low, the memory controller may reduce the frequency to save power.
 Conversely, if the workload increases, the controller can raise the frequency to meet performance demands.

Frequency Scaling:

 The actual process of changing the frequency involves coordination between the memory controller and the
DDR memory modules. The controller adjusts the clock signal sent to the memory modules, and both the
controller and the modules must synchronize to the new frequency to ensure data integrity.

Stabilization:

 After changing the frequency, there is a brief period during which the system stabilizes at the new operating
frequency. This period is critical to ensure that data transfers and memory operations are correctly aligned with
the new clock speed.
 ECC(Error Correcting Code)
 In controller we are having ECC engine which will calculate the check bits and appended to the write data and send
it to the device
 There are 2 types: 1. SECDED => single error correction and double error detection

2. RSECC => reed Solomon error correction code

 SECDED, as name suggest it will correct the single error and detect only multi error bits
 Reed–Solomon codes operate on a block of data treated as a set of elements called symbols. reed–Solomon codes
are able to detect and correct multiple symbol errors.
 To maintain data integrity we are using ECC mechanism.
 The ECC codes are generated by the controller based on the actual WR (write) data. the memory stores both the
write data and the ECC code.
 During a Rd (read) operation, the controller reads both the data and respective ECC code from the memory. the
controller regenerates the ECC code from the received data and compares it against the received ECC code.
 If there is a match, then no errors have occurred. if there are mismatches, the ECC SECDED mechanism allows the
controller to correct any single-bit error and detect double-bit errors.
SCRUBBING FEATURES
Demand Scrubbing:
Demand scrubbing is a feature in DDR5 memory technology that provides a more targeted approach to error correction
compared to traditional patrol scrubbing. Unlike patrol scrubbing, which scans the entire memory periodically, demand
scrubbing is initiated in response to specific requests or triggers, allowing for more efficient use of system resources
and memory bandwidth.
How Demand Scrubbing Works
1. Triggering Mechanism:
Demand scrubbing is typically triggered by the memory controller or the system software based on certain conditions,
such as detecting an error or receiving a specific command. It can also be initiated at regular intervals or based on user-
defined policies.
2. Selective Scanning:
Unlike patrol scrubbing, which scans the entire memory, demand scrubbing focuses on specific areas or blocks of
memory. This selective approach can be more efficient, especially in large memory systems.
3. Error Detection and Correction:
When demand scrubbing is initiated, the memory controller reads the targeted memory locations, checks them
for errors using ECC, and corrects any detected single-bit errors. Multi-bit errors are typically logged and
reported for further action.
4. System Interaction:
Demand scrubbing can be integrated with system-level error handling mechanisms. For instance, the operating
system or firmware can request scrubbing of certain memory regions based on error logs, memory usage
patterns, or thermal conditions.
PATROL SCRUBBING
 Patrol scrubbing is a process where the memory controller periodically reads data from the memory, checks
for errors, and corrects them if necessary.
 This process occurs in the background, independently of the normal read and write operations performed
by the system's CPU or other devices.
How Patrol Scrubbing Works
1. Periodic Scanning:
The memory controller initiates the patrol scrubbing process at regular intervals. This interval can
be configured based on the system requirements and the specific implementation of the memory
controller.
2. Reading Memory:
During patrol scrubbing, the memory controller reads data from each memory location. It doesn't
wait for a read or write request from the CPU; instead, it proactively scans the memory contents.
3. Error Detection:
As data is read from memory, it is checked for errors using error-correcting code (ECC) mechanisms. ECC can
detect and correct single-bit errors and detect (but not correct) multi-bit errors.

4. Error Correction:
If a single-bit error is detected, ECC can correct it on-the-fly. The corrected data is then written back to the
memory, ensuring that the memory content is accurate and free from errors.
5. Logging and Reporting:
Multi-bit errors or uncorrectable errors are logged by the memory controller. Depending on the system's
configuration, these errors might be reported to the operating system, triggering alerts or other corrective
actions.
DDR Initialization
 Initializing DDR memory is a critical process that ensures the memory controller and the DDR memory
modules are properly configured and synchronized. The initialization sequence is essential to establish the
correct operating parameters, timings, and communication protocols.
Steps involved in DDR memory initialization:
1. Power-Up Sequence
Power-On Initialization:
 Apply the power supply voltages to the DDR memory module, ensuring that the power rails (e.g.,
VDD, VDDQ) are within the specified ranges.
Reset Signals:
 Assert the reset signals to the memory controller and the DDR memory. This ensures that the memory
and controller are in a known state.
2. Memory Controller Initialization
Configuration Register Initialization:
 Set up the memory controller’s configuration registers, which include parameters such as memory
size, timings, and controller settings.
PLL Initialization:
 Configure the Phase-Locked Loop (PLL) to generate the appropriate clock frequencies required for
the memory interface.
3. DDR Initialization Sequence
Send Initialization Commands:
 The memory controller sends a series of initialization commands to the DDR memory. These
commands include:
 ZQ Calibration: Perform Zero-Ohm (ZQ) calibration to set the internal impedance of the
memory device. This calibration ensures signal integrity and minimizes noise.
 MR (Mode Register) Configuration: Program the Mode Registers of the DDR memory
modules with the appropriate values for timings, burst lengths, and other configurations.
4. DDR Training and Calibration
Write Leveling:
 Perform write leveling to align the write data strobe (DQS) with the data signals. This step ensures accurate data
writing.
Read Leveling:
 Perform read leveling to align the read data strobe (DQS) with the data signals during read operations. This step
ensures accurate data reading.
DQ Calibration:
 Calibrate the Data Quality (DQ) signals to adjust for any mismatches in the data lines. This ensures data
integrity.
5. DDR Command and Timing Configuration
Program Timing Parameters:
 Configure the timing parameters, such as tCAS (Column Address Strobe to Data), tRAS (Row Address Strobe to
Active), tRP (Row Precharge), and others, according to the memory specification.
Set Refresh Rates:
 Configure the refresh rate and the refresh interval to ensure data integrity over time. This includes setting the
Auto-Refresh (Refresh Interval) and Self-Refresh (Temperature-Compensated Refresh) parameters.
6. Training and Debugging
Training Sequences:
 Execute training sequences to fine-tune the timing parameters and ensure that the data signals are
correctly aligned. This includes read and write leveling, and DQ calibration.
Error Checking:
 Perform error checking and verification using test patterns to ensure that the memory is functioning
correctly. This includes checking for read/write errors, timing violations, and signal integrity issues.
7. Finalize Initialization
Enable DDR Memory:
 Once all initialization steps are completed successfully, enable the DDR memory by de-asserting the
reset signals and starting the memory operations.
Start Normal Operation:
 Begin normal memory operations, including read and write commands, memory refresh cycles, and
data transfers.
MEMORY WIPING

 Memory wiping in DDR5 refers to the process of securely erasing the data stored in DDR5 memory
modules.
 This is crucial for security and data privacy, especially in systems where sensitive information is stored and
must be erased before the system is dismissed, reused, or disposed of.
Memory Wiping Techniques
1. Write Zeroes Command:
 The Write Zeroes command is a simple method where all bits in a specified range of memory are set to
0. This is one of the easiest and most common methods to wipe memory.
 In DDR5, this command can be issued to overwrite all data with zeros.

2. Pattern Write:
 Writing a specific pattern (e.g., 0xAA, 0x55) across the memory. This method is more complex than
writing zeros and is often used to ensure that the data is overwritten with a known pattern.
 CA PARITY
 CA Parity in DDR5 refers to the parity bit used to verify the integrity of the command and address signals sent from
the memory controller to the DRAM.
 Parity is an error-detection mechanism that ensures the accuracy of transmitted data by adding an extra bit that
represents the parity (odd or even) of the transmitted bits.
 The DRAM checks the received command and address signals against the received parity bit.
 If the parity of the command and address signals matches the received parity bit, it means the command or address
received is correct.
 If there is a discrepancy between the parity of the received command and address signals and the received parity bit,
an error is detected.
 The DRAM can then take appropriate actions to handle the error, such as requesting a retransmission or logging the
error, which is mostly fatal error.
CRC(Cyclic Redundancy Check)
Write CRC transaction:
 In memory controller we have CRC engine, where the write data will be taken as input CRC engine and
calculate CRC check code for the write data.
 The write data and check bits are appended in controller and transmitted to device.
 In device we have CRC Engine, where data is encoded with CRC and decoded of data+CRC is done.
 Now the write data has reached the device where CRC engine is given data as input and calculate the check
bits for data and compare the device check bits with received CRC check bits.
 If both check bits are matched , the data is accepted by device.
 If check bit comparison is failed, the device will give an error scenario signal and asks for retry of data.
 Where controller will be checking the status registers of device and upon receiving the error and retry
command, controller will transmit the write data again.
 Like this controller can re-transmit the write data to device up to max.5 transmissions.
 If after retrying for 5 transmissions also we are getting write CRC error, then the controller will inform host
has CRC error through toggling the Alert_n signal.
Read CRC transmission:
 While the controller initiated read transaction , the device will transmit the data by calculating the CRC
for read data .
 The controller while receiving the read data ,it will also calculate the CRC for read data and compare the
received CRC bits with calculated bits .
 If both check bits are matched the read data is accepted and transmitted to host .
 If both check bits are not matched ,then also read data is accepted and transmitted to host with error
indicating to host that the data is corrupted.
 Read CRC retrying is subjected to host ,if host is willing to retry ,the host will send read command to
memory controller.
Basic DDR Write Transaction
Basic DDR Read Transaction
PERFORMANCE

 Latency = first address valid to first Response time

 Bandwidth = Total no of bytes/ Total cycles(complete Txn)
 Efficiency = data Start to end cycle/ Total cycles

Test patterns:
 1write 1 Read
 1write 2 Read
 2 write 1 Read
 1 Write 3 Read
 3 Write 1 Read
 1 Write 4 Read
 4 Write 1 Read
Basic AXI Write Transaction
Basic AXI Read Transaction
Performance Calculation

 Latency = 7-1 =6 ns
 Bandwidth = (4*4 bytes)/7 = 2.28GBPS
 Efficiency = 4/7 = 57%
THANK YOU