ARM 7
CONTROLLER
PrOcEssING
Serial Parallel
⚫ MODEs
processing
Execution - one after the processing
More⚫ than one
other instruction execution takes
place at a time depending
⚫ The biggest problem on the need
with this is that time,
only one ⚫ More than one bit of data
bit of data and
can be can be computed at a time,
computed at acannot and complex programs can
complex programs be be easily split into
segments.
split up into smaller
⚫ Time consumption is very
segments. less compared to serial
⚫ Time consumption is processing
one core to execute
more compared to i.e working is fasta or
processor
parallel processing ⚫ program
computational
The simultaneous multiple
use of
i.e working is slow threads.
more than
▪
CISC: Complex Instruction
Set Computer
▪
RISC: Reduced Instruction
Set Computer
⚫ RISC: Reduce the cycles per instruction at the
cost of the number of instructions per program.
⚫ CISC: The CISC approach attempts to
minimize the number of instructions per
program but at the cost of increase in
number of cycles per instruction.
RISC CISC
Focus on software Focus on hardware
Transistors are used for storing
Transistors are used for more registers
complex Instructions
Code size is large Code size is small
A instruction execute in single clock Instruction take more than one clock
cycle cycle
A instruction fit in one word Instruction are larger than size of one
word
ARM7 TDMI-S
Why is ARM popular?
⚫ ARM is the most popular processors,
particularly used in portable devices due to its
⚫ low power consumption
⚫ Reasonable performance
⚫ Low cost.
⚫ It is very easy to use ARM for quick and efficient
application developments
ARM
ARCHIT
E
CTURE
Features of ARM LPC2148
⚫ The LPC2148 is a 16 bit or 32 bit ARM7 family
based microcontroller and available in a small
LQFP64 package.
⚫ A Low-profile Quad Flat Package (LQFP) is a
surface mount integrated circuit package
format with component leads extending from
each of the four sides.
⚫ On-chip static RAM is 40 kB
⚫ on-chip flash memory is 512 kB
⚫ Programming done via serial port
⚫ Erase and program while application running is
possible
⚫ Hence, greater degree of flexibility
⚫ 1L erase/ write cycles possible
⚫ 20years of data retention
⚫ It takes 400 milliseconds time for erasing the
data in full chip and 1 millisecond time for 256
bytes of programming.
Memory Map
⚫ The microcontroller has a
4GB address space (PC is
32 bits)
⚫ Peripheral registers
are also addressed as
memory locations
Interrupt Controller
• VIC(VECTORED INTERRUPT CONTROLLER) is highly
optimized interrupt controller.
• The VIC is used to handle all the on-chip interrupt
sources from peripherals.
• Each interrupt source is connected to the VIC on a
fixed channel. The application software can connect
these channels to the CPU interrupt lines (FIQ, IRQ)
• In total, ARM supports 32-interrupt request input
• The AMBA (Advance High Performance Bus) is
used for interface vectored interrupt controller
to the ARM7 Core (LPC2148)
• The vector Interrupt Controller (VIC) takes 32-
interrupt request input and assigned them
programably into 3-categories, listed below:
Fast Interrupt Request:
For fast, low latency interrupt handling.
FIQ
FIQ have highest priority followed by interrupt vector
0-31. Only single FIQ source at a time is generally
used in a system
Vectored Interrupt Request:
VIRQ have medium priority.
Vectored IRQ Vectored Interrupt Controller has 32 vectored interrupt slots
out of which 16 slots are used for vector addressing.
Each slot contain vector address register & vector control register
Non-Vectored Request:
Non Vectored IRQ has lowest priority.
Non-Vectored The VIC is capable of handling 16 peripherals as a vectored
interrupt and at least one as an FIQ Interrupt.
IRQ
If in case there are more than 17 interrupt sources on chip,
any extra interrupt can be serviced as a Non-Vectored
Interrupt.
⚫ Vectored interrupt controller has 23-vectored
interrupt slot out of which 16 slots are used in
LPC2148.
⚫ Every slot has set of registers like control &
address register.
⚫ If any of these slot used then these register
should be programmed.
⚫ Slot 0 will have the highest priority and
slot 15 will have lowest priority.
⚫ AMBA- Advanced Microcontroller Bus
Architecture
⚫ AHB – Advanced High-Performance Bus
⚫ Supports the efficient connection of
processors, on-chip memories, off-chip external
memory interface with low peripheral function
⚫ APB- Advanced Peripheral Bus
⚫ For low power peripherals
⚫ VPB- VLSI Peripheral Bus
Pin Connect Block
⚫ Cos, number of I/O pins is limited.
⚫ Allows selected pins to have more than one
function
⚫ MUX allows the connection between the pin
and on-chip peripherals
⚫ The configuration register controls the MUX.
The pin control module with its pin select
registers defines the functionality of the
microcontroller
⚫ Pin function select registers = PINSEL0 and
Pin Select Registers
⚫ Pinsel0 and Pinsel1 are
used for configuring P0
⚫ Pinsel2 configures P2
GPIO
⚫ Fast general purpose parallel IO
⚫ Dynamically configured as I/P or O/P
⚫ For fastest possible I/O timing
⚫ Registers allow setting or clearing any
number of O/P simultaneously
⚫ Individual bits direction control
⚫ All I/O defaults to I/P after reset
⚫ LPC2148 has 46 pins for GPIO purpose, out
of total 64 pins
⚫ LPC2148 has two General Purpose I/O
(GPIO) ports (PORT0 and PORT1)
⚫ To configure a pin on PORT0 as an input or as
an output, write appropriate values to register
IO0DIR (address of 0xE0028008)
⚫ To set (make logical 1) a pin on PORT0, set the
appropriate bit on register IO0SET (address
0xE0028004)
⚫ To read the value of a pin on PORT0, read
appropriate bit on register IO0PIN (address of
0xE0028000) Peripherals
⚫ 5 registers are used to control I/Os
⚫ IOPIN- the current state of the port pins is read
from this register
⚫ IOSET- writing ‘1’ sets high; ‘0’ has no effect
⚫ IOCLR- writing ‘1’ sets low; ‘0’ has no effect
⚫ IODIR-Port pin direction; 0=I/P; 1=O/P
⚫ PINSEL- selects function of pins
Integrated Peripherals
⚫ ADC
⚫ DAC
⚫ Timer
⚫ PWM
⚫ RTC
⚫ WatchDo
g
A/D Converter
⚫ 2, 10 bit Successive Approximation ADC
⚫ ADC0 has 6 channels, ADC1 has 8
channels; Total 14 channels
⚫ Measurement range: oV-Vref
⚫ Minimum 10 bit conversion time: 2.44 µs
⚫ Burst conversion mode for single or
multiple inputs
D/A Converter
⚫ Enables the device to generate a variable
analog output
⚫ 10-bit resolution DAC with a buffered output
⚫ Last output value is held as long as DAC is on
⚫ Output from Zero Volt to Reference Voltage in
1024 steps
⚫ Selectable Conversion speed vs. power
⚫ Settling time 1us, up to 350uA
⚫ Settling time 2.5us, up to 700uA
Timer
⚫ Used to control the sequence of an event or
process
⚫ Timer 0 and 1
⚫ 32-bit Timer
⚫ 32-bit Capture Registers and Capture Pins
⚫ – Four on each timer
⚫ – Capture event can optionally trigger an
interrupt
⚫ 32-bit Match Registers and Match Pins
⚫ – Four on each timer
⚫ – Interrupt, timer reset or timer halt on match
⚫ – Match output can toggle, go high, go low or
Timer Capture
Pulse Width Modulator
⚫ Dedicated 32 bit PWM timer
⚫ Generates interrupts or performs other action
when the specified timer value occurs based
on match register
⚫ Falling and rising edge can be controlled
separately
⚫ PWM outputs all go high at the beginning of each
cycle and go low on a Match
Real Time Clock (RTC)
⚫ Full Clock/Calendar function with alarms
⚫ – Dedicated 32-bit timer with 32-bit pre-scaler
⚫ – Generates its own 32.768 kHz reference clock from any crystal
frequency
⚫ – Counts seconds, minutes, hours, day of month, month, year,
day of week and day of year
⚫ – Can generate an interrupt or set an alarm flag for any
combination of the counters
⚫ Real Time Clock on newer devices
⚫ Can be clocked by a separate 32.768KHz or by prescaler divider
based on VPB clock
⚫ => RTC can run in Power Down mode
⚫ Separate supply pin Vbat which can be connected to battery
or to the 3.3V supply
Watchdog Timer
⚫ Once activated, the Watchdog will reset the
entire chip if it is not fed regularly
⚫ Feed is accomplished by a specific sequence of
data writes
⚫ Watchdog flag allows software to tell that a
watchdog reset has occurred
⚫ Selectable overflow time (µs ... minutes)
⚫ Debug Mode generates an interrupt instead of a
reset
⚫ Secure: watchdog cannot be turned off once it is
I2C Bus serial I/O Controller
⚫ Bidirectional
⚫ Inter IC using 2 wires – Serial Clock line SCL
and Serial Data Line SDL
⚫ Each device recognised by a unique address
⚫ They can operate as 1. Receive only device
(Ex – LCD device)
2. Transmit/ Receive device (Ex – Memory)
⚫ Tx/Rx can operate in master or slave mode,
depending on whether the chip has to initiate
the data transfer or not
I2C Bus serial I/O Controller
⚫ Multi master bus – can be controlled by more
than one bus master connected to it
⚫ Serial clock synchronisation allows devices
with different bit rates to communicate via one
serial line
⚫ Serial clock synchronization can be used as a
handshake mechanism to suspend and resume
serial transfer
⚫ I2C bus is used for test and diagnostic purpose
USB 2.0 Device Controller
⚫ 4-wire serial bus
⚫ Supports communication between host and
peripherals
⚫ Maximum number of peripherals = 127
⚫ Token based protocol
⚫ All transactions initiated by host controller
⚫ Dynamic configuring of the device is possible
⚫ 12Mbits/sec data exchange
⚫ Controller • SI
E • – Decodes the USB data
consists of interface
⚫ Register
stream
⚫ Serial Interface Engine • DM• - Writes data to the
(SIE) A • appropriate EPbetween EP
-Transfer data
⚫ Status Registers and USB RAM
⚫ Endpoint Buffer Memory
(EP)
⚫ DMA Controller
UART
⚫ 2 UARTs - UART0/UART1
⚫ Transmit and receive data lines
⚫ Provides full modem control handshake
interface
⚫ Fractional baudrate generator
⚫ Achieves a baud rate of 115200bps
SSP Serial I/O Controller
⚫ LPC has one serial synchronous Port Controller
⚫ SSP controller is capable of operation on a SPI, 4-
wire SSI or microwire bus
⚫ It can interact with multiple master and slave on
the bus
⚫ However, only a single master and a single
slave can communicate on the bus during a
given data transfer
⚫ SSP supports full duplex transfers, with data
frames of 4 bits to 16 bits of data flowing from
master to the slave and vice versa
SPI Serial I/O controller
⚫ One SPI controller
⚫ Full duplex serial interface
⚫ Designed to handle multiple master and slave
on the bus
⚫ However, only a single master and a single
slave can communicate on the bus during a
given data transfer
⚫ Data transfer is always in bytes
System Control
⚫ Crystal Oscillator
⚫ PLL
⚫ Reset and Wakeup
Timer
Crystal Oscillator
⚫ Range of operation 1MHz-25MHz
⚫ Fosc=oscillator output frequency
⚫ CCLK = ARM Clock Frequency
⚫ When PLL is not connected,
Fosc=CCLK
Phase Locked Loop (PLL)
⚫ 2 PLL modules PLL0 and PLL1
⚫ The PLL0 is used to generate the CCLK clock (system clock)
while the PLL1 has to supply the clock for the USB at the fixed
rate of 48 MHz.
⚫ The PLL0 and PLL1 accept an input clock frequency in the range
of 10 MHz to 25 MHz only.
⚫ The input frequency is multiplied up the range of 10 MHz to 60
MHz for the CCLK and 48 MHz for the USB clock using a
Current Controlled Oscillators (CCO).
⚫ The multiplier can be an integer value from 1 to 32 (in practice,
the multiplier value cannot be higher than 6 on the
LPC2141/2/4/6/8 due to the upper frequency limit of the CPU).
⚫ ARM7 LPC2148 Microcontroller needs two clocks; one is for
its peripherals and other for its CPU.
⚫ CPU works faster with higher frequencies whereas peripheral
needs lower frequency to work with.
⚫ The Peripheral Clock (PCLK) and CPU Clock (CCLK) gets clock
input from a PLL or from external source.
⚫ After RESET, configuration of PLL (Phase Lock Loop) and
VPB (VLSI Peripheral Bus) Divider would be first thing to
do
⚫ PLL unit itself uses CCO (Current Controlled Oscillator) which
operates in the range between 156 MHz to 320 MHz, so there is
additional divider which keeps CCO within its range, while PLL
provides desired frequency.
⚫ Output clock is generated by dividing CCO frequency by 2, 4, 8,
16. Minimum divider is ‘2’ so output of PLL will always have duty
cycle 50% for sure.
⚫ The Peripheral Clock i.e. PCLK is derived from CPU Clock i.e.
APB Bus Divider
⚫ The APB Divider decides the operating frequency
of PCLK.
⚫ Allows power saving when an application does
not require peripheral to run at the full
processor rate.
⚫ During that time, PLL remains active
⚫ The input to APB Divider is CCLK and
output is PCLK.
⚫ By Default PCLK runs at 1/4th the speed of
CCLK.
ARM Architecture
⚫ Typical RISC architecture:
⚫ Large uniform register file
⚫ Load/store architecture
⚫ Simple addressing modes
⚫ Uniform and fixed-length instruction
fields
4
7
Contd…
⚫ Results:
⚫ High performance
⚫ Low code size
⚫ Low power
consumption
⚫ Low silicon area
4
8
Pipeline Organization
⚫ Increases speed –
most instructions executed in
single cycle
⚫ Versions:
⚫ 3-stage (ARM7TDMI and earlier)
⚫ 5-stage (ARMS, ARM9TDMI)
⚫ 6-stage (ARM10TDMI)
4
9
Contd…
□ 3-stage pipeline: Fetch – Decode -
Execute
□ Three-cycle latency,
one instruction per cycle
throughput
i
n
i Fetch Decod Execu
s
t e te
r i+1 Fetc Decod Execute
u h e
i+ Fetc Decod Execute
c 2 h e cycl
t
o e
i
n t t+ t+ t+ t+ 5
0
Operating Modes
⚫ Seven operating
modes:
⚫ User mode
⚫ Privileged/Exception
modes
⚫ System (version 4 and
above)
⚫ FIQ
⚫ IRQ
⚫ Abort
⚫ Undefined 5
1
Contd…
⚫ User mode(USR) is the usual ARM program execution
state, and is used for executing most application
programs.
⚫ Fast Interrupt (FIQ) mode supports a data transfer
or channel process.
⚫ Interrupt (IRQ) mode is used forgeneral-purpose
interrupt handling.
⚫ Supervisor mode(SVC) is a protected mode for the
operating system.
⚫ Abort mode(ABT) is entered aftera data or
instruction Prefetch Abort.
⚫ System mode(SYS) is a privileged user mode for
the operating system.
ARM Registers
⚫ 37 registers 32-bit registers
⚫ 31 general-purpose
⚫ 16 visible, R0 – R15
⚫ Others speed up the exception
process
5
3
Contd…
⚫ Special roles:
⚫ Hardware
⚫ R14 – Link Register
(LR): optionally holds for branch
return address instructions
⚫ R15 – Program Counter
(PC)
⚫ Software
⚫ R13 - Stack Pointer
(SP) 5
4
Contd…
⚫ Current Program Status Register
(CPSR)
⚫ Saved Program Status Register
(SPSR)
⚫ On exception, entering mod
mode:
⚫ (PC + 4) ⭠ LR
⚫ CPSR ⭠ SPSR_mod
⚫ PC ⭠ IV address
⚫ R13, R14 replaced by R13_mod, 5
5
CPSR
Contd…
System & User Supervis Abor IR Undefin
R0 FIQ R0 R0
or R0t R0 Q ed
R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7_fiq R7 R7 R7 R7
R8 R8_fiq R8 R8 R8 R8
R9 R9_fiq R9 R9 R9 R9
R10 R10_fiq R10 R10 R10 R10
R11 R11_fiq R11 R11 R11 R11
R12 R12_fiq R12 R12 R12 R12
R13 R13_fiq R13_svc R13_abt R13_irq R13_und
R14 R14_fiq R14_svc R14_abt R14_irq R14_und
R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC)
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und
5
7