FPGA EMBEDDED CONTROL SYSTEM DESIGN
(Thiết kế hệ điều khiển nhúng FPGA)
CHAPTER 0: COURSE INTRODUCTION
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Course outline
I. Course Objectives
II. Background
III. Recommended Textbooks
IV. Course Evaluation
V. Class Project
VI. Course Tools
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Lecturer/Instructor
Ph.D. LE VAN THUAN
Email: [Link]@[Link]
Office: A9-1601, Mobile: 0987159386
Course Teaching:
• FPGA Embedded Control System Design (Thiết kế hệ điều khiển nhúng FPGA)
• FPGA Design (Lập trình ứng dụng FPGA)
• Digital Transmission (Truyền dẫn số)
• Digital IC Design (Thiết kế vi mạch số)
• Digital Design using VHDL (Thiết kế số dùng VHDL)
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Course Objectives
Provide knowledge and experience in:
• Digital circuit design using an HDL (Verilog)
• HDL simulation
• How to build self checking test benches
• Good practices in digital design verification
• Dataflow and behavior designs
• Design tools commonly used in industry
• How to build a control system on FPGA
Teach you to be able to “think hardware”
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Background
What do you should already know?
Principles of basic digital logic design and control system
• Number representations (unsigned, signed, hex & binary)
• Boole Algebra
• Gate-level design
• Basic logic structures (adder, shifter, counter, MUX, DEMUX, encoder/decoder)
• Finite State Machine (FSM) (possible)
• Basic control blocks (PID, PWM, ...)
• Interactive blocks (UART, SPI, I2C, ...)
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Syllabus
Week Content Notes
1 Chapter 0: Course Introduction (1)
Chapter 1: Introduction of Verilog and FPGA (2)
2, 3 Chapter 2: Verilog Syntax, Structural Verilog and Timing (6)
4, 5 Chapter 3: Testbench, Dataflow and Behavioral Verilog (6)
6, 7, 8 Chapter 4: Finite State Machine (FSM) in Verilog (7)
8 Midterm Exam (2)
9, 10 Chapter 6: Embedded Control System Design (6)
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Course Recommended Textbooks
Lectures
Textbooks
• Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Prentice
Hall, 2003.
• R. Sass and A. G. Schmidt, Embedded Systems Design with Platform FPGAs:
Principles and Practices, Morgan Kaufmann, 2010.
Standards
• IEEE Std.1364-2001, IEEE Standard Verilog Hardware Description Language, IEEE,
Inc., 2001.
Other useful readings
• Michael D. Cilleti, Advanced Digital Design with Verilog HDL, Prentice Hall, 2005
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Course Evaluation
5% Attendance. The compulsory attendance no less than 80%.
5% Homework and Class Quiz
15% Lab Report
15% Midterm Exam
60% Final Project
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Class Project
Work in individually
Design, model, simulate, synthesize on FPGA, and a complex
digital control system
Milestones
• Final demo & report at the exam day in A4-503
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Course Website
Follows the link on:
• Canvas
What the Website will have:
• Lecture Notes
• Attendance Checking and Homework
• Tutorials
• Project Information
• Midterm Solution
• Sample Codes and Exercises
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Course Tools
Industry-standard design tools:
• Modelsim HDL Simulation Tools
• Quartus II
Tutorial
• Quartus II Tutorial
• User’s guide for KIT LP-2900 and DE0-Nano
FPGA KIT
• CPLD/FPGA Digital Logic Design Lab, Model LP-2900
• DE0-Nano Board 11
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