Low-Power Clock Architecture for NPU:
Design & Optimization
Presented by
Rakesh Arumalla (221206), (3rd Year)
Vikas Naik (221233), (3rd Year)
Tharun Nayak (221254), (3rd Year)
Project Supervisor: Prof. G. Seetharaman, C2S Project Investigator
Department of Electronics and Communication Engineering
Indian Institute of Information Technology Tiruchirappalli
Date: 24/02/2025
Overview
Introduction
Literature Review
Proposed Research
References
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Why is Clock Needed for NPUs?
Clock Signal Importance:
• Synchronizes all operations within the NPU
• Ensures data processing occurs in a controlled manner
• Facilitates parallel execution of AI computations
Impact of Clock on Performance:
• Higher clock speeds enable faster neural network processing
• Stability in clock signal reduces computational errors
• Power-efficient clocking extends battery life in embedded AI application
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Parts of the Clock Module
Crystal Oscillator:
• Provides a stable frequency reference
• Determines the base clock signal for the entire system
Phase-Locked Loop (PLL):
• Multiplies and stabilizes the clock frequency
• Reduces phase noise and jitter
Clock Dividers:
• Generate different clock signals from a single source
• Allow multiple clock domains in NPUs
03/03/2025 C2S Project Presentation
Parts of the Clock Module
Clock Gating:
• Reduces power consumption by disabling unused clock signals
Dynamic Frequency Scaling (DFS):
• Adjusts clock speed based on processing demand to optimize
power
Clock Monitors:
• Ensure stability, detect anomalies, and maintain timing accuracy
Clock Distribution
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Proposed Crystal Frequency
Crystal Frequency Use Case Example Chips
Qualcomm Snapdragon NPU,
19.2 MHz Mobile SoCs, Edge AI
Google Edge TPU
NVIDIA Jetson AI Chips, ARM AI
24 MHz Consumer AI Chips, GPUs
Cores
25 MHz Datacenter NPUs, Networking Broadcom AI Switches, Google TPU
Huawei Kirin NPU, MediaTek AI
26 MHz 5G AI, Embedded AI
Chips
40 MHz High-Speed AI Tesla Dojo, IBM AI Chips
Custom Edge AI NPUs, High-
50 MHz Custom AI ASICs
Performance AI
NVIDIA Tensor Cores, AMD Instinct
100 MHz Server AI, GPUs
AI
125 MHz High-Speed Compute Intel Habana Gaudi AI Accelerator
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PLL-Architecture
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Types of Architectures
PLL Type Power Consumption Jitter Performance Complexity Best Use Case
General-purpose,
Charge-Pump PLL (CP-PLL) Medium Low jitter High microcontrollers, mixed-
signal SoCs
Ultra-low-power IoT, Edge
All-Digital PLL (ADPLL) Very Low Medium High
AI, processors
Power-sensitive
Digital PLL (DPLL) Low Medium Medium
applications, IoT
RF circuits, energy-
Injection-Locked PLL (ILPLL) Extremely Low High jitter Low
harvesting systems
Ultra-low power, clock
Sub-Sampling PLL (SSPLL) Low Very Low (Best) High
generators for ADCs
Fractional-N PLL Medium Low jitter High RF transceivers, telecom
Hybrid PLL (Analog + High-speed, low-power
Low Very Low Medium
Digital) mixed-signal designs
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C2S Project Presentation 8
Differences in Traditional PLL and ILO-PLL
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Proposed Design for PLL
ADPLL + ILO (All-Digital PLL + Injection-Locked Oscillator)
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Differences between Two stage Design and Single Stage-
(MOD-30)
Factor ILO + ADPLL (5×6) ✅ ILO + Mod-30 Counter ❌
Switching Activity Lower ✅ (Optimized loop operation) Higher ❌ (Frequent toggling)
Leakage Power Lower ✅ (Optimized transistors) Higher ❌ (Large counter logic)
Jitter Performance Better ✅ Higher Jitter ❌
Clock Stability Higher Stability ✅ More Noise ❌
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Components in ADPLL(All-digital phase-locked loop)
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Proposed Design Outline
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References
List 5 to 10 References
In IEEE Reference format
List in Alphabetical order
Example:
1. G. Eason, B. Noble, and I. N. Sneddon, “On certain integrals of Lipschitz-Hankel type involving products of Bessel
functions,” Phil. Trans. Roy. Soc. London, vol. A247, pp. 529–551, April 1955.
Author Name, Author Name, “Title of the Paper”, Journal Name, Vol. No: xy, Issue No: xy, pp. xyz-xyz , Month
Year.
Thank You
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