8086 Microprocessor Pin Diagram and 8088

Pin Diagram
• 8086 Microprocessor Pin Diagram and 8088
Pin Diagram has been designed to work in two
operating modes :
• Minimum Mode Configuration
• Maximum Mode Configuration
• The Minimum Mode Configuration of 8086 is
used for a small systems with a single processor
and Maximum Mode Configuration of 8086 is
for medium size to large systems, which often
include two or more processors.
• Figure shows the 8086 Microprocessor Pin
Diagram and 8088 Pin Diagram in minimum as
well as maximum mode.
• Both are packaged in 40-pin dual-in-line
package (DIPS).
• The 8086 is a 16-bit microprocessor with a 16-bit
data bus.
• The 8088 is a 16-bit microprocessor with an 8-bit
data bus.
• The pin-diagram shows, the 8086 has pin
connections AD0-AD15, and the 8088 has pin
connections AD0-AD7. There is one difference in
one of the control signals. The 8086 has an M/IO’
pin, and the 8088 has an I0/M’ pin.
• Another difference appears on pin 34 of both
chips : on the 8086 it is a BHE’/S7 pin, while on the
8088 it is a SS0’ bar pin.
Difference between 8086 and 8088
8086 Architecture
8088 Architecture
• The 8086 microprocessor has a segmented
memory architecture, which means that memory
is divided into segments that are addressed using
both a segment register and an offset.
• The segment register points to the start of a
segment, while the offset specifies the location of
a specific byte within the segment. This allows
the 8086 microprocessor to access large amounts
of memory, while still using a 16-bit data bus.
• The 8086 microprocessor has two main
execution units: the execution unit (EU) and
the bus interface unit (BIU).
• The BIU is responsible for fetching instructions
from memory,while the EU executes the
instructions. The BIU also manages data
transfer between the microprocessor and
memory or I/O devices.
• Memory segmentation:
• In order to increase execution speed and
fetching speed, 8086 segments the memory.
• Its 20-bit address bus can address 1MB of
memory, it segments it into 16 64kB segments.
• The internal architecture of Intel 8086 is
divided into 2 units: The Bus Interface Unit
(BIU), and The Execution Unit (EU).
 Bus Interface Unit (BIU)
• It provides the interface of 8086 to external
memory and I/O devices via the System Bus. It
performs various machine cycles such as
memory read, I/O read, etc. to transfer data
between memory and I/O devices.
• BIU performs the following functions are as
follows
• It generates the 20-bit physical address for
memory access.
• It fetches instructions from the memory.
• It transfers data to and from the memory and
I/O.
• Maintains the 6-byte pre-fetch instruction
queue(supports pipelining).
 Instruction Pointer (IP)

• It is a 16-bit register. It holds offset of the next

instructions in the Code Segment.
• IP is incremented after every instruction byte is
fetched.
• IP gets a new value whenever a branch instruction
occurs.
• CS is multiplied by 10H to give the 20-bit physical
address of the Code Segment.
• The address of the next instruction is calculated by
using the formula CS x 10H + IP.
• Example:
• CS = 4321H IP = 1000H
• then CS x 10H = 43210H + offset = 44210H
Here Offset = Instruction Pointer(IP) This is the
address of the next instruction.
• Code Segment register: (16 Bit register): CS holds
the base address for the Code Segment. All
programs are stored in the Code Segment and
accessed via the IP.
• Data Segment register: (16 Bit register): DS holds
the base address for the Data Segment.
• Stack Segment register: (16 Bit register): SS holds
the base address for the Stack Segment.
• Extra Segment register: (16 Bit register): ES holds
the base address for the Extra Segment.
 Execution Unit (EU)
• The main components of the EU are General
purpose registers, the ALU, Special purpose
registers, the Instruction Register and
Instruction Decoder, and the Flag/Status
Register.
8086 has four 16-bit general purpose regist
ers
• AX, BX, CX, and DX which store intermediate
values during execution. Each of these has two
8-bit parts (higher and lower).
• AX register: (Combination of AL and
AH Registers)
It holds operands and results during
multiplication and division operations.
• BX register: Combination of BL and BH Registers
• CX register: (Combination of CL and CH Registers)
It holds the count for instructions like a loop,
rotates operation.
• DX register: (Combination of DL and DH Registers)
It is used with AX to hold 32-bit values during
multiplication and division.
• Arithmetic Logic Unit (16-bit): Performs 8 and
16-bit arithmetic and logic operations.
• Special purpose registers (16-bit): Special
purpose registers are called Offset registers
also. Which points to specific memory
locations under each segment.
• Stack Pointer: Points to Stack top. Stack is in Stack
Segment, used during instructions like PUSH, POP,
CALL, RET etc.
• Base Pointer: BP can hold the offset addresses of
any location in the stack segment. It is used to
access random locations of the stack.
• Source Index: It holds offset address in Data
Segment.
• Destination Index: It holds offset address in Extra
Segment.
8086 Pin Diagram
It has 2 GND's (Ground) as the circuit's complexity demands a large amount of current flowing through the circuits, and multiple
grounds help in dissipating the accumulated heat.
 Difference Between TEST’ and READY Pin

• TEST’: input is examined by the ‘‘Wait’’ instruction.

If the TEST input is LOW execution continues,
otherwise the processor waits in an ‘‘Idle’’ state.
This input is synchronized internally during each
clock cycle on the leading edge of CLK.
• READY: is the acknowledgement from the addressed
memory or I/O device that it will complete the data
transfer. The READY signal from memory/IO is
synchronized by the 8284A Clock Generator to form
READY. This signal is active HIGH.
• HOLD/HOLDA: HOLD indicates that another master
has been requesting a local bus .This is an active
high(1). The microprocessor receiving the HOLD
request will issue HLDA (high) as an acknowledgement
in the middle of a T4 or T1 clock cycle.
• DT/R’ : Data Transmit/Receive. This pin is required in
minimum mode, that want to use an 8286 or 8287
data bus transceiver. The direction of data flow is
controlled through the transceiver.
• DEN’: Data enable. This pin is provided as an output
enable for the 8286/8287 in a minimum system which
uses transceiver. DEN is active low(0) during each
memory and input-output access and for INTA cycles.
Control signals for all operations are generated by decoding S’ 2, S’1 and S’0 using
8288 bus controller.
Types of Operations
 Minimum Mode Operation
• The 8086 microprocessor operates in minimum
mode when MN/MX’ = 1.
• In minimum mode,8086 is the only processor in
the system which provides all the control signals
which are needed for memory operations and I/O
interfacing.
• The other components which are transceivers
8286, latches 8282, 8284 clock generator, 74138
decoder, memory and i/o devices are also present
in the system.
 Minimum Mode Operation
• The address bus of 8086 is 20 bits long. By this
we can access 220 byte memory i.e. 1MB . Out
of 20 bits, 16 bits A0 to A15(or 16 lines) are
multiplexed with a data bus. By multiplexing, it
means they will act as address lines during the
first T state of the machine cycle and in the
rest, they act as data lines. A16 to A19 are
multiplexed S3 to S6 and BHE’ is multiplexed
with S7.
 Minimum Mode Operation
• 8282 (8 bits) latch They are used to separate
the valid address from the multiplexed
Address/data bus by using the control signal
ALE, which is connected to strobe(STB) of
8282. The ALE is active high signal. Here three
such latches are required because the address
is 20 bits.
 Minimum Mode Operation
• 8286 (8 bits) transceivers They are used to
separate the valid data from multiplexed
add/data bus. Two such transceivers are
needed because the data bus is 16 bits long.
8286 is connected to DT/R’ and DEN’ signals.
They are enabled through the DEN signal .The
direction of data on the data bus is controlled
by the DT/R’ signal. DT/R’ is connected to T
and DEN’ is connected to OE’.
 Minimum Mode Operation
• 8284 clock generator is used to provide the clock.
• Control signals for all operations are generated by
decoding M/IO’, RD’, WR’. They are decoded by 74138 3:8
decoder.
• INTR and INTA :
When INTR = 1,then there is an interrupt to 8086 by other
devices for their service. When INTA’= 0,then it indicates
that the processor is ready to service them.
• The bus request is made by other devices using the HOLD
signal and the processor acknowledges them using the
HLDA output signal.
Read Cycle Timing Diagram Minimum Mode
8086
 Read Cycle Timing Diagram Minimum Mode
8086
• At T1 state ALE =1 ,this indicates that a valid address is
latched on the address bus and also M / IO’= 1, which
indicates the memory operation is in progress.
• In T2, the address is removed from the local bus and is
sent to the addressed device.
• When RD’ = 0 , the valid data is present on the data bus.
• During T2 DEN’ =0, which enables transceivers and DT/R’ =
0 ,which indicates that the data is received.
• During T3, data is put on the data bus and the processor
reads it.
 Read Cycle Timing Diagram Minimum
Mode 8086
• The output device makes the READY line high. This means the output device
has performed the data transfer process. When the processor makes the
read signal to 1, then the output device will again tristate its bus drivers.
•
Tri-state buffers are commonly used in bus-based systems, where multiple
devices are connected to the same bus and need to share it. For example, in
a computer system, multiple devices such as the CPU, memory, and
peripherals may be connected to the same data bus. To ensure that only
one device can transmit data on the bus at a time, each device is equipped
with a tri-state buffer. When a device wants to transmit data, it activates its
tri-state buffer, which connects its output to the bus and allows it to
transmit data. When the transmission is complete, the device deactivates its
tri-state buffer, which disconnects its output from the bus and allows
another device to access the bus.
Write Cycle Timing Diagram Minimum
Mode 8086
 Write Cycle Timing Diagram Minimum
Mode 8086
• At T1 state ALE =1 ,this indicates that a valid address is latched on
the address bus and also M / IO’= 1, which indicates the memory
operation is in progress.
• In T2, the processor sends the data to be written to the addressed
location.
• The data is buffered on the bus until the middle of T 4 state.
• The WR’=0 becomes at the beginning of T2.
• The BHE’ and A0 signals are used to select the byte or bytes of
memory or I/O word.
• During T2 DEN’ =0, which enables, transceivers and DT/R’ = 1 ,which
indicates that the data is transferred by the processor to the
addressed device.
 Maximum mode Operation

• In this we can connect more processors to

8086 (8087/8089).
• 8086 max mode is basically for
implementation of allocation of global
resources and passing bus control to other
coprocessor(i.e. second processor in the
system)
• The resources which are common to all
processors are known as global resources.
 Maximum mode Operation

• When MN/ MX’ = 0 , 8086 works in max mode.

• Clock is provided by 8284 clock generator.
• 8288 bus controller- Address from the address bus is latched into
8282 8-bit latch. Three such latches are required because address
bus is 20 bit. The ALE(Address latch enable) is connected to
STB(Strobe) of the latch. The ALE for latch is given by 8288 bus
controller.
• The data bus is operated through 8286 8-bit transceiver. Two such
transceivers are required, because data bus is 16-bit. The
transceivers are enabled through the DEN signal, while the direction
of data is controlled by the DT/R signal. DEN is connected
to OE’ and DT/ R’ is connected to T. Both DEN and DT/ R’ are given
by 8288 bus controller
 Advantages of max mode of 8086
• It helps to interface more devices like [Link] interface
is also called a closely coupled co-Processor
configuration. In this 8086 is called as the host and 8087
as Co-processor.
• It supports multiprocessing, Therefore it helps to
increase the efficiency.
• The 8087 was the first floating-point coprocessor for the
8086 series of microprocessors. The purpose of the 8087
was to increase calculations for floating point
operations, such as add, sub, multiply, divide, and
square root.