Drag and Atmospheric Neutral

Density Explorer
(DANDE)
Command and Data Handling
(CDH)

Preliminary Design Review

September 13th, 2007

Brandon Gilles (EE)

James Gorman (ECE)
Eric McIntyre (ECE)
Gabe Thatcher (EE)
 Detailed Schedule
Program Schedule
Spring Summer Fall Spring Summer Fall
07 07 07 08 08 08
SCR ♦ Concept Design, Requirements Definition

Prelim. Design & ♦

Breadboard
PDR Design Documentation, Analysis,
♦ Breadboard Verification
Flat-sat Build Electrically equivalent
♦
satellite on a lab bench
EDU & Vibe Test ♦
CDR EDU, Analysis, Flat Sat, Verification at 50% ♦
Proto Qualification Build ♦
PQR Proto-Qualification Unit at 80%, Verification at 90% ♦
Proto Qualification Testing ♦
FCR Proto-Qualification Unit at 100%, Verification at 100%, as-built documentation →
DANDE CDH PDR ECEN 4610 Capstone Laboratory
 Responsibilities of CDH

• Monitor and manage health of satellite.

• Record and pre-process data from science
subsystems.
• Provide command and control functionality.
• Manage the operating modes of satellite.
– Science
– Safe
– Separation
– Spin-up

DANDE CDH PDR ECEN 4610 Capstone Laboratory 3

 Scope of Implementation
• Developing the Flat Satellite version of the CDH system
– Full Hardware and software functionality
– Boards do not have size constraints
– Standard practice for satellite development
• Size constrained boards come after Flat-Sat completion

• The CDH portion of the

DANDE Flat-Sat is the
scope of this capstone
project

Here is the Flat-Sat of the

Naval Academy’s ‘Pcsat’

[Link]
DANDE CDH PDR ECEN 4610 Capstone Laboratory 4
 Outline of Approach

• Distributed architecture
– Main “Flight Computer”
• 32-bit Atmel AVR
• Linux 2.6 Kernel
– Subsystem microcontrollers
• 8-bit Atmel AVRs

DANDE CDH PDR ECEN 4610 Capstone Laboratory 5

 CDH Block Diagram

DANDE CDH PDR ECEN 4610 Capstone Laboratory 6

 Subsystem and Instrument Interfaces

• Interfaces to the satellite are all through the subsystem

microcontrollers
– Subsystem microcontrollers are responsible for collecting and buffering
salient science and health data from the subsystem instruments.
– The Flight Computer polls the subsystem microcontrollers periodically
for data
• Extent of Subsystem Development
– The CDH team shall provide an AVR reference design to the subsystem
designer
• AVR hardware reference design
• AVR driver package (in C)
– Beyond this reference design, no further subsystem development is in
the scope of this project

DANDE CDH PDR ECEN 4610 Capstone Laboratory 7

 Division of Labor

• Brandon Gilles • Eric McIntyre

– Project Manager – REA - 32-bit Software
– REA - 32-bit Hardware – Architecture
– REA - Linux Kernel – Analysis and Design
• James Gorman – Implementation
– REA - 8-bit Hardware and Software • Gabriel Thatcher
Reference Design – REA - Memory Voting Logic
– REA - Watch Dog and Long Dog
– REA - Subsystem Hardware
Circuitry
Interfacing
– 32-bit Hardware

• Across the board

– 32-bit Software Analysis, Design and Implementation

REA - Responsible Engineering Authority

DANDE CDH PDR ECEN 4610 Capstone Laboratory 8
 Implementation, Schedules, and Risk Assessment

• High-Level Systems Software

• Flight Computer Hardware and Drivers
• Subsystem Computer Hardware and Drivers

DANDE CDH PDR ECEN 4610 Capstone Laboratory 9

 High-Level Systems Software

DANDE CDH PDR ECEN 4610 Capstone Laboratory 10

 Implementation

The following methods will ensure successful

implementation:
• Adherence to the rational process
• Detailed documentation during all workflows including
requirements, analysis, and design
• Object-oriented design for applicable systems
• Coding during the implementation workflow will be
performed in development environments provided by
the chip manufacturer.

DANDE CDH PDR ECEN 4610 Capstone Laboratory 11

 Schedule

DANDE CDH PDR ECEN 4610 Capstone Laboratory 12

 Schedule

DANDE CDH PDR ECEN 4610 Capstone Laboratory 13

 Risk Assessment

• Risk: Failure to define requirements.

– Consequences: Interfaces may not be clear or specified to
users. Software may require rework, patches, or be unusable.
– Mitigation: Following the rational process, meeting regularly
with users, documenting, and holding regular reviews with the
other subsystem leads
• Risk: Failure to build compatible software with specified
hardware.
– Consequences: Software will be unusable.
– Mitigation: When defining implementation iterations each
build will be tested on target hardware, which is available, to
be considered usable.

DANDE CDH PDR ECEN 4610 Capstone Laboratory 14

 Flight Computer Hardware

DANDE CDH PDR ECEN 4610 Capstone Laboratory 15

 Flight Computer: Implementation

• The flight computer needs to be able to process large

amounts of data
• It also needs to have support for high level code.
– This is so the other systems can write algorithms in an easy to use
object-oriented language
– This is also so that there is protected memory so a bug in one
piece of code does not wipe out everything else

DANDE CDH PDR ECEN 4610 Capstone Laboratory 16

 Flight Computer: Implementation

• The AVR32 processor will be used

– This is a 32 bit RISC processor
– High performance
• Pipelined with superscalar out-of-order execution
• Instruction and data cache
– Internal DRAM controller
– Fully supported in the Linux 2.6 kernel
– Extensive integrated peripherals

DANDE CDH PDR ECEN 4610 Capstone Laboratory 17

 Flight Computer: Implementation

• The Linux operating system needs to be loaded out of a non-volatile

memory which can be rewritten during flight
– This can either be a parallel access NAND Flash chip or a SPI NAND Flash device
• 64 MB of non-volatile memory is required for science mission data
– This will be in the form of an SD card
• This system requires RAM for the same reasons a PC requires RAM
– Needs a place to execute code out of
– Needs a place to store variables
• Either SRAM or DRAM will be used
– Decision will be made based on amount of RAM required and ease of
implementation
– Other factors such as radiation tolerance may affect decision

DANDE CDH PDR ECEN 4610 Capstone Laboratory 18

 Flight Computer: Risk Assessment

• Make or Buy Decision for flight computer:

– Make:
• Getting a processor with external memory running is a very
difficult task
• In addition the processor is only available in a 256 pin BGA
package
• Processor speed requires board design with signal integrity in
mind (150MHz max)
– Buy:
• Prevents Radiation Mitigation Techniques
– Memory Voting Circuit

DANDE CDH PDR ECEN 4610 Capstone Laboratory 19

 Subsystems Hardware and Drivers

DANDE CDH PDR ECEN 4610 Capstone Laboratory 20

 Implementation

• Most of the subsystems need a way to interface their

hardware to the central processor/ data bus
• An Atmel AVR 8-bit microcontroller will be used
• The microcontroller requires little hardware support for
external circuitry
• Many I/O pins and peripheral hardware available for
interfacing to subsystems

DANDE CDH PDR ECEN 4610 Capstone Laboratory 21

 Implementation

• Each subsystem will need to be able to write their own

software to interface to their hardware
• This requires that low level drive be written to handle the
following operations:
– Manipulate digital I/O pins
– Communicate using the UART or SPI module
– Sample analog signals using the internal converter
– Use the timers to sample data at the proper rate
– React to commands from the central processor
– Transmit data back to the main computer

DANDE CDH PDR ECEN 4610 Capstone Laboratory 22

 Flight Computer: Risk Assessment

• The hardware system involves very few risks

• The software risks involves writing the software in an
extensible and easy to use way
– Ther e is no protected memory so all other code can cause faults in the system
– The proper libraries may not be provided.
• Libraries Currently Planned
– Real Time Clock
– Timer
– UART
– SPI
– Analog Input

DANDE CDH PDR ECEN 4610 Capstone Laboratory 23

 Schedule

DANDE CDH PDR ECEN 4610 Capstone Laboratory 24

 Backup Slides

DANDE CDH PDR ECEN 4610 Capstone Laboratory 25

 DANDE Background Information

• Drag and Atmospheric Neutral Density Explorer

– A Low-Cost Small-Satellite Program for Neutral Density, Wind, and Composition
Research with Applications Space Weather Models
– DANDE measures atmospheric density variations
– DANDE will also provide coefficient of drag data
– DANDE weighs 110 lb (50 kg), and is 18” (0.46 m) in diameter.
– DANDE spins at 10 RPM to provide gyroscopic stability for instrument pointing, and ease of
attitude determination and control.
– DANDE uses the aluminum shell halves of its structure as a receive antenna, and a piano
wire embedded in Delrin as a transmit antenna.
– DANDE will use a novel aerobraking mechanism to quickly descend from a common 310-
370 miles (500-600 km) orbit to its science orbit at 220 miles (350 km)

DANDE CDH PDR ECEN 4610 Capstone Laboratory 26

 Exploded View

DANDE CDH PDR ECEN 4610 Capstone Laboratory 27

 Communications Analysis
• Data volume:
bits/sample sample rate samples / day bits / day
NMS (Neutral Mass Spectrometer) 4,192 bits 0.01667 Hz 1,440 6,036,480 bits
ACC (Accelerometer) 32 bits 0.2 Hz 17,280 552,960 bits
PRS (Pressure Sensor) 32 bits 0.2 Hz 17,280 552,960 bits
Health and Status (Engineering) data 4,096 bits 0.00028 Hz 24 98,304 bits

• Communications passes: TOTAL DATA / DAY 7,240,704 bits

– Average pass length: 247 seconds ( @ start of mission)

– ~2 passes per day at Boulder CO (40°N)
– At 9600bps, we can downlink ~1,968,000 bits per pass
– Takes ~4 passes to downlink one day’s data
• Communications trade studies (in-progress):
– Adding ground stations
• Space Grant Colleges in Hawaii, Puerto Rico
• Can downlink all data using 3 ground stations
– Microwave (2.4GHz) communications equipment
• Currently increasing TRL at home institution
– Potential use of local high-gain antenna facility
• 2 x 60’ steerable dishes ([Link]
DANDE CDH PDR ECEN 4610 Capstone Laboratory
 Functional Block Diagram
FOV Wiring Harness
360°

Acc
EPS Photovoltaics 30W CDH SFT ACC Acc
A cc
x4 RAM TBD OS
Battery

2
I C I/O
Inhibit
LV electrical

Battery A Scheduling
B
interface

Control
x4 14.4V
14.4V CPU Acc
Inhibit
4AH
4AH
Comm Acc
AVR32
ABS Regulation Control
ADCS

Serial I/O

Acc
Science

SEP SSD NMS

TBD Instrument
Lightband assy.

Mech1

RTC
Instrument
Control FOV
THM Coatings, Insulation 32° x 1°
Mech2
Control Sensors

COM ADC Control

Torque
rod A
Satellite Sep Plane (SSP)

Tx
Tx Ant

FOV
90° 70cm Torque Instrument
38.4kbps Control Mag (3- rod A
axis) FOV
TNC 32° x 1°
Rx
Rx Ant

FOV 2m
Horizon

Horizon
Crossin

Crossin
Sensor

Sensor

90°
9.6kbps
g

DANDE CDH PDR FOV 2° Laboratory

ECEN 4610 Capstone FOV 2° 29