UNIT-III

GATE LEVEL
DESIGN
Topics
• Logic gates and other complex
gates
• Switch logic
• Alternate gate circuits
• Time delays
• Driving large capacitive loads
• Wiring capacitances
• Fan-in and fan-out, Choice of layers
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 NMOS Gate
• construction
NMOS devices in series implement a NAND function

A•B A B F
A 0 0 1
0 1 1
B
1 0 1
1 1 0

•NMOS devices in parallel implement a NOR function

A B F
A+B 0 0 1
A B
0 1 0

1 0 0

1 1 0
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 PMOS Gate
•
construction
PMOS devices in parallel implement a NAND function

A B F
0 0 1
A B
0 1 1
1 0 1
A•B 1 1 0

•PMOS devices in series implement a NOR function

A B F

0 0 1
B
0 1 0
A
1 0 0

A+B 1 1 0
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 Parasitics and
Performance
• Consider the
following
layout: a
• What is the
impact on
parasitic b
c
performance
s of
– At point a (VDD
rail)?
– At point b (input)?
– At Point c (output)?

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 Parasitics and
Performance
• a - power
supply
connections a
– capacitance -
no effect on
delay c
– resistance -
increabses delay (see
p. 135)
• minimize by
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 Driving Large
Loads
• Off-chip loads, long wires, etc. have high
capacitance
• Increasing transistor size increases driving ability
(and speed), but in turn increases gate
capacitance
• Solution: stages of progressively larger transistors
– Use nopt = ln(Cbig/Cg).
– Scale by a factor of a=e

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 Summary: Static
CMOS
• Advantages
– High Noise Margins (VOH=VDD, VOL=Gnd)
– No static power consumption (except for leakage)
– Comparable rise and fall times (with proper sizing)
– Robust and easy to use
• Disadvantages
– Large transistor counts (2N transistors for N
inputs)
• Larger area
• More parasitic loading (2 transistor gates on each
input)
– Pullup issues
• Lower driving capability of P transistors
• Series connections especially problematic
• Sizing helps, but increases loading on gate inputs
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 Alternatives to Static
CMOS
• Switch Logic
• nmos
• Pseudo-nmos
• Dynamic Logic
• Low-Power
Gates

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 Switch
Logic
• Key idea: use transistors as
switches
• Concern: switches are bidirectional
A B

AND

OR

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 Switch Logic - Pass
Transistors
• Use n-transistor as
IN: OUT:
“switches” VDD-Vtn
• “Threshold problem”
– Transistor switches off when Vgs <VDD
A:
Vt VDD
– VDD input -> VDD-Vt output
• “pecial gate needed to “restore”
values

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 Switch Logic - Transmission
Gates
• Complementary transistors - n and p
• No threshold problem
• Cost: extra transistor, extra control
input
• Not a perfect conductor!
A’
A’

A
A
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 Switch Logic Example - 2-1
MUX

IN

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 Charge
• Sharing
Consider transmission gates in series
– Each node has parasitic capacitances
– Problems occur when inputs change
to redistribute charge
– Solution: design network so there is always a
path from VDD or Gnd to output

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 Aside: Transmission Gates in
Analog
• Transmission Gates
work with analog values, too!
• Example:
Voltage-Scaling D/A
Converter

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 NMOS
Logic
• Used before CMOS was
widely available
• Uses only n transistors
– Normal n transistors in pull- Passive Pullup Device:
down network depletion Mode
n-transistor (Vt < 0)
– depletion-mode n
OUT
transistor (Vt < 0) used for
pull-up Pulldown
Network
– "ratioed logic" required
• Tradeoffs:
– Simpler processing
– Smaller gates
– higher power!
– Additional
design
considerations
for ratioed logic
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 Pseudo-nmos
Logic
• Same idea, as nmos, but use
p- transistor for pullup
• "ratioed logic" required
for proper design (more Passive Pullup Device:
about this next) P-Transistor
• Tradeoffs:
OUT
– Fewer transistors -> smaller
Pulldown
gates, esp. for large Network
number of inputs
– less capacitative load on
gates
that drive inputs
– larger power consumption
– less noise margin (VOL > 0)
– additional design
considerations due to ratioed
logic
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 Rationed Logic for Pseudo-
• Approach:
nmos
– Assume VOUT=VOL =0.25*VDD
– Assume 1 pulldown transistor is on
OUT
– Equate currents in p, n transistors Pulldown
Idp
Network
– Solve for ratio between sizes of p, n Idn
transistors to get these conditions
– Further necessary
calculations series for
connections
W
1  I pnn
Idn
2 k' n L n V

gs,n
tn  V  2 1
2
Wp

p Lp 2 V
gs,p tp

 Vds,pV  V2ds,p
 (EQ 3  21)

Wp k'
Lp (EQ 3  22)  Assu min g V DD 
Wn  3.9
Ln 3.3V
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 DCVS
Logic
• DCVS - Differential
Cascode Voltage
Switch
• Differential inputs,
outputs
• Two pulldown OUT OUT’

networks A
OUT OUT’
A’
• Tradeoffs Pulldown Pulldown B’
B C’
– Lower capacitative Network Network

loading than static CMOS C

– No ratioed logic needed

– Low static
power
consumption
– More transistors
– More signals to
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 Dynamic
Logic
• Key idea: Two-step operation
– precharge - charge CS to logic
high
– evaluate - conditionally discharge CS
Storage Node

C S
• Control - precharge clockSignal Pulldown
Precharge Storage
Capacitance
Network
f B
A
C


Precharge Evaluate Precharge

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 Domino
Logic
• Key idea: dynamic gate +
inverter
• Cascaded gates - “monotonically

increasing” CS

Pulldown
Network
B

 C

in4

x1

x2

x3
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 Domino Logic
Tradeoffs
• Fewer transistors -> smaller gates
• Lower power consumption than pseudo-
nmos
• Clocking required
• Logic not complete (AND, OR, but no NOT)

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