CE-215T: Digital
Logic Design
Jawaid Shabir
jshabir@[Link]
Computer Engineering Department
WEEK NO:10
sequential
circuits
Sequential Circuits
• Combinational
• The outputs depend only on the current input values
• It uses only logic gates
• Sequential
• The outputs depend on the current and past input values
• It uses logic gates and storage elements
• Example
• Vending machine
• They are referred to as finite state machines since they have a
finite number of states
Sequential Circuits
Block Diagram Sequential Circuit Types
• Memory elements can store binary • Synchronous
information • The circuit behavior is determined
• This information at any given time by the signals at discrete instants
determines the state of the circuit at of time
that time • The memory elements are affected
only at discrete instants of time
• A clock is used for synchronization
• Memory elements are affected only
with the arrival of a clock pulse
• If memory elements use clock pulses
in their inputs, the circuit is called
• Clocked sequential circuit
Sequential Circuits
• Asynchronous Clock
• The circuit behavior is • It emits a series of pulses with
determined by the signals at precise pulse width and precise
any instant in time interval between consecutive
• It is also affected by the pulses
order in the inputs change • Timing interval between the
corresponding edges of two
consecutive pulses is known as
the clock cycle time, or period
Flip-Flops
• They are memory elements • Can keep a binary state until an
• They can store binary information input signal to switch the state
is received
• There are different types of flip-
flops depending on the number
of inputs and how the inputs
affect the binary state
Latches
• The most basic flip-flops SR Latch with NOR GATE
• They operate with signal levels
• The flip-flops are constructed from
latches
• They are not useful for synchronous
sequential circuits
• They are useful for asynchronous
sequential circuits
Latches
SR Latch with NOR SR Latch with NAND GATE
S set
R reset
Q 1, Q' 0 set state
Q 0, Q' 1 reset state
S 1, R 1 undefined, Q and Q' are set to 0
In normal conditions , avoid S 1, R 1
Latches
SR Latch with NAND SR Latch with Control Input
S set
R reset
Q 0, Q' 1 set state
Q 1, Q' 0 reset state
S 0, R 0 undefined, Q and Q' are set to 1
In normal conditions , avoid S 0, R 0
Logic Symbol
SR Latch
Timing Diagram of SR Latch
Timing Diagram of SR Latch
D Latch
D Latch
Notes
• Latches are based on combinational gates (e.g. NAND, NOR)
• Latches store data even after data input has been removed
• S-R latches operate like cross-coupled inverters with control inputs (S = set, R =
reset)
• With additional gates, an S-R latch can be converted to a D latch (D stands for
data)
• D latch is simple to understand conceptually
• When C = 1, data input D stored in latch and output as Q
• When C = 0, data input D ignored and previous latch value output at Q
• Next time: more storage elements!
Why FFs
• Latches respond to trigger levels on control inputs
• Example: If G = 1, input reflected at output
• Difficult to precisely time when to store data with latches
• Flip flips store data on a rising or falling trigger edge.
• Example: control input transitions from 0 -> 1, data input appears at output
• Data remains stable in the flip flop until until next rising edge.
• Different types of flip flops serve different functions
• Flip flops can be defined with characteristic functions.
CLOCK SIGNALS
• The clock signal must be periodic • The clock signal can be used as an
while the enable input is not enable input, while an enable input
necessarily be a periodical signal. can not always be a clock signal.
• The frequency of clock signal must
be stable, while the frequency of an
enable input can be changed.
• The signals in all Logic circuits are
edge triggered, while there is no
edge-triggering in enable inputs.
CLOCK SIGNALS
• In synchronous systems, the exact times at which any output can change states are
determined by a signal commonly called the CLOCK.
• The clock signal is generally a rectangular pulse train or square wave as shown in following
figure:
• It should be noted that the clock need not be the perfectly symmetrical waveform. The
main requirement is that the clock be perfectly periodic and stable.
IDEAL CLOCK
WAVE FORM
COMPARISON BETWEEN CLOCK AND ENABLE SIGNALS:
• Both enable and clock signals are used for synchronizing the operation of
Electronic Circuits.
• For active high values of clock and enable inputs. 1 binary input activates
circuit operation. 0 input deactivates circuit operation.
• For active low clock and enable inputs, 0 activates the circuit operation and 1
deactivates circuit operation.
Edge Triggered Flip Flop.
• A flip flop that changes state at either the rising (positive) or the falling
(negative) edge of a clock is termed as an edge triggered flip flop.
SR flip flop
SR flip flop
SR flip flop
Clock
Time
Q
CLOCKED D- FLIP-FLOP
• There are two disadvantages of RS –FF
• The generation of two signals to derive a FF
• The forbidden or invalid state.
• These disadvantages are completely avoided by D-FF
• The operation of D-FF is much simpler. It has only one input D in addition to the clock or
enable input.
• If there is a High on the D input, when and active clock signal is applied, The FF sets and
stores a 1 bit.
• If there is Low on the D input when active clock signal is applied, the FF Resets and stores a 0
bit.
• If clock disables the circuit operation then FF performs No Change operation.
• The circuit of RS – FF is modified in following manner and this type of construction is known
as D-flip flop.
CLOCKED D- FLIP-FLOP
CLOCKED D- FLIP-FLOP
Time
Clock
D
Q
CLOCKED D- FLIP-FLOP
• Stores a value on the positive edge of Clock
• Input changes at other times have no effect on output
APPLICATION OF D-FF
• In digital systems data normally store in group of bits that represent numbers,
codes or other information.
• The idea of storage is illustrated in following figure
• Each of the four parallel data lines is connected to the D input of a flip flop.
• Since the entire clock inputs are connected to the same clock, the data on the
D input are stored simultaneously by the flip flop on the positive edge of the
clock.
• Storing a 4-bit word
• Negative Edge D-FF
• Do yourself.
Edge-Triggered J-K Flip-Flop
• The JK flip flop works very similar to RS flip flop. The only difference is that this FF has no
invalid state.
• The outputs toggle (change to the opposite state) when both J and K inputs are HIGH.
POSITIVE EDGE TRIGGERED JK FLIP FLOP
Edge-Triggered J-K Flip-Flop
• The basic circuit of positive edge triggered JK –FF is identical to the positive edge
triggered RS-FF which two important additions,
• The Q output is connected back to the input of AND gate that is receiving K input
• The output is connected back to the input of AND gate that is receiving J input.
• The cross coupling from outputs to inputs changes the RS –FF into a JK – FF.
• The process S input is now labeled J and the previous R input is labeled K.
Edge-Triggered J-K Flip-Flop
• The basic circuit of positive edge triggered JK –FF is identical to the positive edge
triggered RS-FF which two important additions,
• The Q output is connected back to the input of AND gate that is receiving K input
• The output is connected back to the input of AND gate that is receiving J input.
• The cross coupling from outputs to inputs changes the RS –FF into a JK – FF.
• The process S input is now labeled J and the previous R input is labeled K.
Edge-Triggered J-K Flip-Flop
• Two data inputs, J and K APPLICATION OF JK-FF:
Counters
• J -> set, K -> reset, if J=K=1 then toggle output Frequency Divider
Positive Edge-Triggered T Flip-Flop
• Another type of flip flop is the T (Toggle) flip
flop. This FF is obtained from a JK type when
input J and K are connected to provide a single
input designated by T.
• The T flip flop, therefore, has only two
conditions:
• When T = 0, FF performs No Change operation
• When T = 1, FF performs Toggle operation.
Positive Edge-Triggered T Flip-Flop
Clock
Q
SYNCHRONOUS & ASYNCHRONOUS INPUTS
• Basically, there are two types of inputs for all types of FFs.
1. Synchronous inputs
2. Asynchronous inputs
1. Synchronous inputs
• Synchronous inputs are those inputs. Which can only on the output of Flip Flop, when an active signal is
generated from clock input
• In the construction of different types or flip flops, R, S, J, K, D and T are all synchronous inputs.
2. Asynchronous inputs
• Most Flip Flops also have one or more asynchronous inputs which operate independently of the synchronous
inputs and clock inputs.
• PRESET and CLEAR inputs are used in the construction of flip flop and these inputs are known as Asynchronous
inputs.
• These Asynchronous inputs can be used to set the FF to the 1 state (PRESET) or clear the FF to the 0 state
(CLEAR) at any time, regardless of the conditions at the other inputs.
• The most common designation for asynchronous inputs is PRE (short for PRESET) and CLR (short for CLEAR)
• PRE and CLR will be represented for active – High inputs and and will indicate their active Low status.
Asynchronous Inputs
• Asynchronous inputs operate independently of the synchronous inputs and clock
• Set the FF to 1/0 states at any time.
Asynchronous Inputs
POSITIVE EDGE TRIGGERED JK-FF WITH PRESET & CLEAR INPUT
POSITIVE EDGE TRIGGERED JK-FF WITH PRESET & CLEAR INPUT
Flip Flop Applications
Flip Flop Applications
Flip Flop Applications
PULSE TRIGGERED (MASTER SLAVE ) FLIP FLOP
• Another class of flip flop is the pulse-triggered or Master-Slave.
• The term pulse–triggered means that data are entered into the flip flop on the leading edge of the clock
pulse but the output does not reflect the input state until the trailing edge of the clock pulse.
• The input must be setup prior to the clock pulse ‘s leading edge, but the output is postponed until the trailing
edge of the clock pulse.
• The major restriction of the pulse–triggered flip-flop is that the data input must not change while the clock
pulse is high, because the flip-flop is sensitive to any change of input levels during this time.
PULSE TRIGGERED (MASTER-SLAVE ) JK FLIP FLOP;
• As with the edge–triggered flip flops, there are different types pulse triggered flip flops: RS, D, JK, and,T.
• The JK is by far the most commonly available in integrated circuits form.
• The logic symbol of the JK master-slave flip-flop is shown in fig.
• The key to identifying a pulse–triggered (master-slave) flip flop by its logic symbol is the ANSI / IEEE
postponed output symbol ( ) at the outputs
• This symbol means that the output does not change until the occurrence of the clock edge following the
triggering edge.
PULSE TRIGGERED (MASTER SLAVE ) FLIP FLOP
PULSE TRIGGERED (MASTER SLAVE ) FLIP FLOP
Clock
Clock
J
K
Q
Master-Slave D Flip Flop
• Consider two latches combined together
• Only one Clock value active at a time
• Output changes on falling edge of the clock
D C Q Q’
0 1 0 1
1 1 1 0
X 0 Q0 Q0’
Notes
• Flip flops are powerful storage elements
• They can be constructed from gates and latches!
• D flip flop is simplest and most widely used
• Asynchronous inputs allow for clearing and presetting the flip flop
output
• Multiple flops allow for data storage
• The basis of computer memory!
• Combine storage and logic to make a computation circuit
• Next time: Analyzing sequential circuits.