0% found this document useful (0 votes)
53 views11 pages

Y86 Sequential Execution Overview

Uploaded by

kinzasarfaraz521
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
53 views11 pages

Y86 Sequential Execution Overview

Uploaded by

kinzasarfaraz521
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Y86 Sequential

Implementation
Roll no # 136 Ayesha Siddiqui
Introduction to Y86

What is Y86?
A simplified educational architecture based on x86 to
teach computer architecture concepts.
Includes a subset of x86 instructions for easier
understanding and implementation.
Used in courses to illustrate how a processor executes
instructions.
SEQ(SEQUENTIAL EXECUTION)
The SEQ (Sequential Execution) is
used in a system where Y86 is
sequentially implemented . In this
model, the Y86 processor executes
one instruction at a time, progressing
through a fixed sequence of steps.
SEQ Hardware
Key Hardware Components

[Link] Counter (PC):


Used to fetch and execute instructions sequentially.
Holds the address of the next instruction to be executed.

[Link] Memory:
Stores the program instructions.

[Link]:
Provide storage for temporary data and operands.
A set of general-purpose registers (%eax, %ebx, etc.) used for computations.

[Link] Logic Unit (ALU):


Performs arithmetic and logical operations (e.g., addition, subtraction, AND, OR).
Takes inputs from the registers or immediate values and produces a result.
[Link] Memory:
Used for reading and writing data during load and store
operations. Sore operand

[Link] Unit:
Decodes instructions and generates control signals for other
hardware components. Guides the flow of data through different
stages.

[Link] Code Register:


•Purpose: Stores flags (e.g., Zero, Negative, Overflow) to evaluate
conditions for branch instructions.
SEQ STAGES

Instruction fetch

Instruction Decode

Instruction
Execute

Memory Access

Write back
•Stage 1 (Fetch): Fetch the instruction from memory.

•Stage 2 (Decode): Decode the instruction and prepare the operands.

•Stage 3 (Execute): Execute the operation (e.g., performing the addition).

•Stage 4 (Memory): Access memory (if necessary, but not used here).

•Stage 5 (Write-back): Write the result back to the register (e.g., store the result in
%eax).

Example
.pos 0
irmovl $5, %eax
irmovl $3, %ebx
addl %ebx, %eax
halt
Explanation of Stages:
[Link] 1 (Fetch and Decode):
•irmovl $5, %eax: Fetch the constant 5 from memory and load it into %eax.
•irmovl $3, %ebx: Fetch the constant 3 from memory and load it into %ebx.
[Link] 2 (Execute):
•addl %ebx, %eax: This is the Execute stage, where the contents of %ebx are added to
%eax. After execution, %eax will hold the value 8 (i.e., 5 + 3).
[Link] 3 (Memory):
•There are no memory accesses required in this example since it’s only dealing with registers. If
there were any memory operations (e.g., loading from or storing to memory), they would occur in
this stage.
[Link] 4 (Write-back):
•The result of the addition (8 in %eax) would be written back to the register during the
Write-back stage. However, in this case, the addition is done directly in registers, so this stage is
implicitly covered by the instruction.
[Link] 5 (Halt):
•halt: This instruction stops the program after completing all previous stages.

You might also like