Nand2

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 1

 Netlist
.SUBCKT nand2test DVDD DVSS a b out
*.PININFO a:I b:I out:O DVDD:B DVSS:B
MM2 out a net35 DVSS nch_svt_mac l=16.0n nfin=3 m=2
MM3 net35 b DVSS DVSS nch_svt_mac l=16.0n nfin=3 m=2
MM1 out b DVDD DVDD pch_svt_mac l=16.0n nfin=3 m=3
MM0 out a DVDD DVDD pch_svt_mac l=16.0n nfin=3 m=3
.ENDS

Sp
.inc '[Link]'
.protect
.lib '/home/yllo/Executable_Package/Collaterals/Tech/iPDK/N16ADFP_iPDK/models/toplevel.l'top_tt
.unprotect
X1 DVDD DVSS a b out nand2
vvdd DVDD 0 0.8
vgnd DVSS 0 0
.temp 25
VA a 0 pulse(0 0.8 0 0.1n 0.1n 0.4n 1n )
VB b 0 pulse(0 0.8 1n 0.1n 0.1n 0.9n 2n )
.tran 0.1n 5n
.op
.option post
.option captab
.end

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 2

 Layout

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 3

 Waveview

Pre-sim

Post-sim
Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 4
 比較表

tr tf td tp pwr

Pre-sim 21.3p 17.7p 61.4p 1.5n 266n

Post-sim 24.5p 36.2p 79.1p 1.5n 240n

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 5

 D-type Flip Flop with Preset and
Clear

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 6

 D-type Flip Flop with Preset and
Clear
SP
.inc 'dff_w_pre_clr.netlist'
.protect
.lib
'/home/yllo/Executable_Package/Collaterals/Tech/iPDK/
N16ADFP_iPDK/models/toplevel.l'top_tt
.unprotect
X1 clk clr DVSS data nq q pre DVDD dff_w_pre_clr
vvdd DVDD 0 0.8
vgnd DVSS 0 0
.temp 25
VIN1 CLK 0 pulse(0 0.8 0n 0.1n 0.1n 0.4n 1n)
VIN2 Data 0 pulse(0 0.8 0.5n 0.1n 0.1n 0.7n 1.6n)
VIN3 PRE 0 pwl(0n 0.8v 3.6n 0.8v 3.7n 0v 4.7n 0v 4.8n
0.8v 10n 0.8v R)
VIN4 CLR 0 pwl(0n 0.8v 7.4n 0.8v 7.5n 0v 8.5n 0v 8.6n
0.8v 10n 0.8v R)
.tran 0.1n 10n
.op
.option post
.option captab
.end
Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 7
 Netlist
.SUBCKT nand3 DVDD DVSS a b c out .SUBCKT dff_w_pre_clr clk clr DVSS data nq q pre DVDD
*.PININFO a:I b:I c:I out:O DVDD:B DVSS:B *.PININFO clk:I clr:I data:I pre:I nq:O q:O DVDD:B DVSS:B
MM2 out c DVDD DVDD pch_svt_mac l=16n nfin=2 m=1 XI4 DVDD DVSS q net18 clr nq / nand3
MM1 out b DVDD DVDD pch_svt_mac l=16n nfin=2 m=1 XI3 DVDD DVSS pre net20 nq q / nand3
MM0 out a DVDD DVDD pch_svt_mac l=16n nfin=2 m=1 XI2 DVDD DVSS net20 clk net15 net18 / nand3
MM5 net13 c DVSS DVSS nch_svt_mac l=16n nfin=2 m=1 XI1 DVDD DVSS net22 clr clk net20 / nand3
MM4 net14 b net13 DVSS nch_svt_mac l=16n nfin=2 m=1 XI0 DVDD DVSS pre net15 net20 net22 / nand3
MM3 out a net14 DVSS nch_svt_mac l=16n nfin=2 m=1 XI5 DVDD DVSS net18 data net15 / nand2
.ENDS .ENDS

.SUBCKT nand2 DVDD DVSS a b out

*.PININFO a:I b:I out:O DVDD:B DVSS:B
MM1 out b DVDD DVDD pch_svt_mac l=16n nfin=2 m=1
MM0 out a DVDD DVDD pch_svt_mac l=16n nfin=2 m=1
MM3 net11 b DVSS DVSS nch_svt_mac l=16n nfin=2 m=1
MM2 out a net11 DVSS nch_svt_mac l=16n nfin=2 m=1
.ENDS

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 8

 Layout

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 9

 Pre-sim
Pre-sim pwr:904n

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 10

 Post-sim
Post-sim pwr:4.44u

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 11

 比較表

tr tf td tp pwr

Pre-sim 16.8p 5.69p 39.8p 1n 960n

Post-sim 32.7p 30p 51.4p 1.02n 4.46u

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 12

 Demultiplexers

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 13

 Demultiplexers

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 14

 Netlist
.SUBCKT nand3 DVDD DVSS a b c out .SUBCKT demultiplexers DVDD DVSS a b d0 d1 d2 d3 e
*.PININFO a:I b:I c:I out:O DVDD:B DVSS:B *.PININFO a:I b:I e:I d0:O d1:O d2:O d3:O DVDD:B
MM2 out c DVDD DVDD pch_svt_mac l=16n nfin=2 m=1 DVSS:B
MM1 out b DVDD DVDD pch_svt_mac l=16n nfin=2 m=1 MM5 net19 e DVDD DVDD pch_svt_mac l=16n nfin=2
MM0 out a DVDD DVDD pch_svt_mac l=16n nfin=2 m=1 m=1
MM5 net13 c DVSS DVSS nch_svt_mac l=16n nfin=2 m=1MM3 net18 b DVDD DVDD pch_svt_mac l=16n nfin=2
MM4 net14 b net13 DVSS nch_svt_mac l=16n nfin=2 m=1 m=1
MM3 out a net14 DVSS nch_svt_mac l=16n nfin=2 m=1 MM0 net21 a DVDD DVDD pch_svt_mac l=16n nfin=2
.ENDS m=1
Sp
.inc '[Link]' XI6 DVDD DVSS a b net19 d3 / nand3
.protect
XI5 DVDD DVSS net18 a net19 d2 / nand3
.lib '/home/yllo/Executable_Package/Collaterals/Tech/iPDK/N16ADFP_iPDK/models/toplevel.l'top_tt
.unprotect
XI4 DVDD DVSS net21 b net19 d1 / nand3
X1 DVDD DVSS a b d0 d1 d2 d3 e Demultiplexers XI3 DVDD DVSS net21 net18 net19 d0 / nand3
vvdd DVDD 0 0.8
vgnd DVSS 0 0 MM4 net19 e DVSS DVSS nch_svt_mac l=16n nfin=2 m=1
.temp 25
VE E 0 pwl(0 0 0.1n 1.8 1.1n 1.8 1.2n 0 ) MM1 net21 a DVSS DVSS nch_svt_mac l=16n nfin=2 m=1
VA A 0 pwl(0 0 3.2n 0 3.3n 1.8 5.3n 1.8 5.4n 0 )
VB B 0 pwl(0 0 2.2n 0 2.3n 1.8 3.3n 1.8 3.4n 0 4.4n 0 4.5n 1.8 5.5n 1.8 5.6n 0)
MM2 net18 b DVSS DVSS nch_svt_mac l=16n nfin=2 m=1
.tran 0.1n 6n
.op
.ENDS
.option post
.option captab
.end

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 15

 Layout

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 16

Pre-sim pwr:259n Pre-sim

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 17

Post-sim pwr:2.06u
Post-sim

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 18

 比較表

tr tf td tp pwr

Pre-sim 15.6p 10.8p 39p 5.56n 320n

Post-sim 14.6p 22.6p 67.2p 5.56n 2.06u

Mixed-Signal Integrated Circuit Lab YU-TIEH CHEN 19