STES’s

Sinhgad College of Engineering

Vadgaon, Pune-411041
Accredited with Grade ‘A’ by NAAC

Faculty Orientation Workshop

on
BE (E&TC) Revised 2019 Course

Subject: VLSI Design and

Technology
under the aegis of
Board of Studies E&TC, Savitribai Phule Pune
University,
[14-16 July 2022]
Pune
Organized by
Department of Electronics &
Application Specific Integrated
Circuits
 UNIT 5 : Application Specific Integrated
Circuits
Syllabus
 Design Flow, Cell design specifications,
 Spice simulation, AC and DC analysis, Transfer
Characteristics, Transient responses, Noise analysis, Lambda
rules,
 Fabrication methods of circuit elements, Layout of cell,
Library cell designing for NAND &NOR, Circuit Extraction,
 Design Rule Check, Electrical Rule Check, Layout Vs.
Schematic, Post-layout Simulation and Parasitic extraction,
 Design Issues like Antenna effect, Electro migration effect,
Cross talk and Drain punch through, Timing analysis
 Justification on CO-PO mapping
Course Objective:
To discuss ASIC issues and PLD architectures with advanced features .
Course Outcomes :
Analyze various issues and constraints in design of an ASIC.
CO-PO-PSO Mapping:

PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2

CO
C40 3 2 3 2 3 2 -- -- 3 2 2 1 3 3
1.5
Teaching Methodology
 Virtual lab links
Sr. Name of the Virtual Lab by Virtual lab Link
No. experiment
INDIAN INSTITUTE OF
1. MOSFET Characteristics TECHNOLOGY GUWAHATI
[Link]
MOSFET_simulator.html

INDIAN INSTITUTE OF
2. CMOS Inverter TECHNOLOGY GUWAHATI
[Link]
CMOS_simulator.html

INDIAN INSTITUTE OF
3. Dynamic characteristics of TECHNOLOGY GUWAHATI
[Link]
2-input gates using NgSpice LogicGates_simulator.html
(i) NAND, (ii) NOR,
(iii) XOR (iv) XNOR
 Application-Specific
Integrated Circuit (ASIC)
An Application-Specific Integrated
Circuit (ASIC) is an integrated
circuits (IC) customized for a particular
use, rather than intended for general-
purpose use.

For example, a chip designed to run in a

digital voice recorder is an ASIC.
ASIC Design Flow
Cell Design Specifications
 The cell used in the hard IP or soft IP.
 Function of the cell.
performance of the cell.(including
various parameters used in ckt)
Power consumption.
Process features.
 SPICE Simulations
Circuit elements:
Resistors, Capacitors, Inductors,
Dependant and Independent current and
voltage sources, Switches and Active
devices
Analysis modes:
DC analysis, Transient analysis, AC small
signal analysis, Pole-zero analysis, Small
signal distortion analysis, sensitivity
analysis, Noise analysis, Temperature
analysis.
Syntax of circuit elements
a)Resistor: Rxx n1 n2 value
b)Capacitor: Cxx n1 n2 value
c)Inductor: Lxx n1 n2 value
d)Voltage source: Vxx n1 n2<DC>DC-
value
e)Current source: Ixx n1 n2<DC>DC-value
f)MOSFET: Mxxx nd ng ns nb<model
name>
Va 1 4 DC 5V
Vb 3 4 DC 5V
Vdd 2 4 DC 5V
M1 5 1 2 2 PMOS L=100 W=50
M2 5 3 2 2 PMOS L=100 W=50
M3 5 1 6 6 NMOS L=100 W=25
M4 6 3 4 4 NMOS L=100 W=25
.DC Va 0 5 0.5
.DC Vb 0 5 0.5
.PROB EV(5)
.END
Layout Design
Lamda Rules (Lambda)
rules
 Layout Design Rules (Micron-180nm)
Sr. No. Description Rule (um)
1 Metal width 0.3
2 Metal Spacing 0.3
3 Polysilicon width 0.18
4 Polysilicon Spacing 0.3
5 VIA( Width and Length) 0.2 X 0.2
6 VIA Spacing 0.3
7 Contact( Width and Length) 0.2 X 0.2
8 Contact Spacing 0.2
9 Oxide width 0.4
10 Oxide Spacing 0.3
11 Nwell width and spacing 1.0
 Design Rule Check
Design rule violation.

The design rule specifications check all

the rectangles, polygons and layers from
layout database meet all the
manufacturing process rules.

Cadence Dracula.
 Electrical Rule Check
ERC Rules check for things such as:
Floating gates.
Wrong transistor connections (Source and
Drain connected together for instance).
Floating interconnect, Metal, Poly.
Shorted Drain & Source of a MOS.
No substrate- or well contact
Distance of MOS to next substrate / well
contact too large.
 Design issues like
Antenna Effect
 In modern IC technologies the fine feature size is
typically achieved using the plasma process.
These plasma processes leads to the design
issues known as Antenna Effect.
 The antenna effect is also known as Plasma
induced gate oxide damage.
 Crosstalk
In CMOS logic circuits the high
impedance of the output mode makes
the circuits very sensitive to the
crosstalk effects.

The capacitive crosstalk also affects to

the signal integrity.

Crosstalk does not results in breakdown

but affects the performance of gate
 Electro migration Effect
 The current density in a metal layers is limited in
the VLSI chips. This effect of current density in
metal layers or the chip is called as electro
migration effect.
 The electro migration effect mainly depends upon
the temperatrure, crystal lattice structure and
current density in the wire.
 Metal particals flow with electrons.
 Drain Punch Through
 When the drain is at high enough voltage with
respect to the source, the depletion region around
the drain may extend to the source, thus causing
current to flow irrespective of the gate voltage.
 Punch through is a destructive phenomenon if it is
not properly taken care it completely destroy the
IC.
Two types of punch through effects

Surface punch through :

when depletion reigons touch each other
at the surface.

Subsurface punch through :

when the depletion regions touch each
other below the surface.
CMOS Fabrication
CMOS transistors are fabricated on silicon
wafer
Lithography process similar to printing
press
On each step, different materials are
deposited or etched
Easiest to understand by viewing both top
and cross-section of wafer in a simplified
manufacturing process
Detailed Mask Views
Six masks
n-well
n well

Polysilicon
n+ diffusion Polysilicon

p+ diffusion
n+ Diffusion

Contact
Metal p+ Diffusion

Contact

Metal
Fabrication
Chips are built in huge factories called fabs
Contain clean rooms as large as football
fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2
(oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed
wafer
Strip off SiO2

p substrate
Oxidation
Grow SiO2 on top of Si wafer

SiO2

p substrate
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic
polymer
Softens where exposed to light

Photoresist
SiO2

p substrate
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist

Photoresist
SiO2

p substrate
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of
steps

n well
p substrate
 Polysilicon
Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon
layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate
Polysilicon Patterning
Use same lithography process to pattern
polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate
Self-Aligned Process
Use oxide and masking to expose where
n+ dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and
n-well contact

n well
p substrate
P-Diffusion
Similar set of steps form p+ diffusion
regions for pMOS source and drain and
substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate
Metalization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving
wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate
Stick Diagrams

A stick diagram is used to plan the layout of

transistor cell. It uses ‘sticks’ or lines to represent
the devices and conductors.

It is necessary to define the direction and

metalization of the power supply, round, input and
output.

Rules for drawing stick diagram are :

[Link] and round lines run horizontally in metal 1.
[Link] i/p and o/p are accessible from top or bottom
of the cell and will be in metal 2 running vertically.
Fig : Stick diagram conventions
Gate layouts

(1)Inverter

The placing of the components in the schematic

the stick diagram is changed and hence, the
layout of the circuit will change accordingly.

(a)schematic (b)stick
diagram
Fig (c) shows the physical layout of inverter which is
drawn in tanner tool.

(c)layout
(2)Two input NAND Gate
(3)Three Input NAND Gate
(4)Two input NOR Gate
(5)Transmission Gate
 Assignments to be conducted
1. Explain with neat diagrams the various NMOS fabrication technology.

2. Draw the fabrication steps of CMOS transistor and explain its operation in
detail.

3. Explain significance of DRC, ERC and LVs.

4. Spice code for DC, AC, transient analysis.

Thank You!!!