Lecture 16:
CAMs, ROMs,
PLAs
Outline
Content-Addressable Memories
Read-Only Memories
Programmable Logic Arrays
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 2
CAMs
Extension of ordinary memory (e.g. SRAM)
– Read and write memory as usual
– Also match to see which words contain a key
adr data/key
read
CAM match
write
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 3
10T CAM Cell
Add four match transistors to 6T SRAM
– 56 x 43 λ unit cell
bit bit_b
word
cell
cell_b
match
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 4
CAM Cell Operation
Read and write like ordinary SRAM
For matching:
CAM cell
clk weak
– Leave wordline low
miss
row decoder
address match0
– Precharge matchlines match1
– Place key on bitlines match2
– Matchlines evaluate read/write column circuitry
match3
Miss line data
– Pseudo-nMOS NOR of match lines
– Goes high if no words match
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 5
Read-Only Memories
Read-Only Memories are nonvolatile
– Retain their contents when power is removed
Mask-programmed ROMs use one transistor per bit
– Presence or absence determines 1 or 0
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 6
ROM Example
4-word x 6-bit ROM Word 0: 010101
– Represented with dot diagram Word 1: 011001
– Dots indicate 1’s in ROM Word 2: 100101
weak
A1 A0 pseudo-nMOS Word 3: 101010
pullups
2:4
DEC
ROM Array
Y5 Y4 Y3 Y2 Y1 Y0
Looks like 6 4-input pseudo-nMOS NORs
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 7
ROM Array Layout
Unit cell is 12 x 8 λ(about 1/10 size of SRAM)
Unit
Cell
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 8
Row Decoders
ROM row decoders must pitch-match with ROM
– Only a single track per word!
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 9
Complete ROM Layout
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 10
PROMs and EPROMs
Programmable ROMs
– Build array with transistors at every site
– Burn out fuses to disable unwanted transistors
Electrically Programmable ROMs
– Use floating gate to turn off unwanted transistors
– EPROM, EEPROM, Flash
Source Gate Drain Polysilicon
Floating Gate
Thin Gate Oxide
(SiO2)
n+ n+
p bulk Si
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 11
Flash Programming
Charge on floating gate determines Vt
Logic 1: negative Vt
Logic 0: positive Vt
Cells erased to 1 by applying a high body voltage so
that electrons tunnel off floating gate into substrate
Programmed to 0 by applying high gate voltage
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 12
NAND Flash
High density, low cost / bit
– Programmed one page at a time
– Erased one block at a time
Example:
– 4096-bit pages
– 16 pages / 8 KB block
– Many blocks / memory
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 13
64 Gb NAND Flash
64K cells / page
4 bits / cell (multiple Vt)
64 cells / string
– 256 pages / block
2K blocks / plane
2 planes
[Trinh09]
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 14
Building Logic with ROMs
Use ROM as lookup table containing truth table
– n inputs, k outputs requires 2n words x k bits
– Changing function is easy – reprogram ROM
Finite State Machine
– n inputs, k outputs, s bits of state
– Build with 2n+s x (k+s) bit ROM and (k+s) bit reg
inputs
n ROM Array
inputs outputs
2n wordlines
n ROM k k
DEC
s s
state
k outputs
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 15
Example: RoboAnt
Let’s build an Ant
Sensors: Antennae L R
(L,R) – 1 when in contact
Actuators: Legs
Forward step F
Ten degree turns TL, TR
Goal: make our ant smart enough to
get out of a maze
Strategy: keep right antenna on wall
(RoboAnt adapted from MIT 6.004 2002 OpenCourseWare by Ward and Terman)
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 16
Lost in space
Action: go forward until we hit something
– Initial state
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 17
Bonk!!!
Action: turn left (rotate counterclockwise)
– Until we don’t touch anymore
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 18
A little to the right
Action: step forward and turn right a little
– Looking for wall
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 19
Then a little to the left
Action: step and turn left a little, until not touching
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 20
Whoops – a corner!
Action: step and turn right until hitting next wall
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 21
Simplification
Merge equivalent states where possible
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 22
State Transition Table
S1:0 L R S1:0’ TR TL F
00 0 0 00 0 0 1
Lost 00 1 X 01 0 0 1
00 0 1 01 0 0 1
01 1 X 01 0 1 0
RCCW 01 0 1 01 0 1 0
01 0 0 10 0 1 0
Wall1 10 X 0 10 1 0 1
10 X 1 11 1 0 1
11 1 X 01 0 1 1
Wall2 11 0 0 10 0 1 1
11 0 1 11 0 1 1
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 23
ROM Implementation
16-word x 5 bit ROM L, R TL, TR, F
S1 S0 L R
ROM
S'1:0
0000
0001 S1:0
0010
0011
0100
0101
4:16 DEC
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
S1' S0' TR'TL' F'
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 24
ROM Implementation
16-word x 5 bit ROM L, R TL, TR, F
S1 S0 L R
ROM
S'1:0
0000
0001 S1:0
0010
0011
0100
0101
4:16 DEC
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
S1' S0' TR'TL' F'
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 25
PLAs
A Programmable Logic Array performs any function
in sum-of-products form.
Literals: inputs & complements
Products / Minterms: AND of literals AND Plane OR Plane
Outputs: OR of Minterms bc
ac
ab
Minterms
abc
Example: Full Adder abc
abc
s abc abc abc abc abc
cout ab bc ac
a b c s cout
Inputs Outputs
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 26
NOR-NOR PLAs
ANDs and ORs are not very efficient in CMOS
Dynamic or Pseudo-nMOS NORs are very efficient
Use DeMorgan’s Law to convert to all NORs
AND Plane OR Plane AND Plane OR Plane
bc bc
ac ac
ab ab
abc abc
abc abc
abc abc
abc abc
a b c a b c
s cout s cout
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 27
PLA Schematic & Layout
AND Plane OR Plane
bc
ac
ab
abc
abc
abc
abc
a b c
s cout
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 28
PLAs vs. ROMs
The OR plane of the PLA is like the ROM array
The AND plane of the PLA is like the ROM decoder
PLAs are more flexible than ROMs
– No need to have 2n rows for n inputs
– Only generate the minterms that are needed
– Take advantage of logic simplification
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 29
Example: RoboAnt PLA
Convert state transition table to logic equations
S1:0 L R S1:0’ TR TL F
00 0 0 00 0 0 1
00 1 X 01 0 0 1
00 0 1 01 0 0 1
01 1 X 01 0 1 0
01 0 1 01 0 1 0
01 0 0 10 0 1 0
10 X 0 10 1 0 1
10 X 1 11 1 0 1
11 1 X 01 0 1 1 TR S1 S0
11 0 0 10 0 1 1 TL S0
11 0 1 11 0 1 1 F S1 S0
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 30
RoboAnt Dot Diagram
AND Plane OR Plane
S1' S1 S0 LS1 LRS0 S0
S1
S 0' R LS1 LS0
S0
TR S1 S0 LS 0
TL S0 LS1
R
F S1 S0
LRS 0
LS1
S1 S 0
S1 S0 L R
S1 ' S0 ' TR TL F
20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 31