COMPUTER

ORGANIZATI
ON AND
ARCHITECTU
RE (COA)
Ms. Umang Kant
AP, KIET, CSE-AIML Department
Ph.D Research Scholar, DTU,
CSE
CONTENTS
1. Bus Arbitration Techniques
1. Centralized Arbitration
1. Daisy Chaining Method
2. Polling Method
3. Independent Request Method

2. Distributed Arbitration

2. Bus and Memory Transfer

1. Using Multiplexer
2. Using Three State Gates

3. Numerical on bus and memory transfer

 UNIT 01
INTRODUCTI
ON
BUS ARBITRATION
TECHNIQUES
There are 2 types of bus arbitration techniques
1. Centralized Arbitration (commonly used)
2. Distributed Arbitration
CENTRALIZED ARBITRATION
•In centralized bus arbitration, a single bus arbiter performs the
required arbitration. The bus arbiter may be the processor, or a
separate controller connected to the bus.
•There are three different arbitration schemes that use the
centralized bus arbitration approach. There schemes are:
a. Daisy chaining
b. Polling method
c. Independent request
 •It is simple and cheaper method. All masters make use
of the same line for bus request.
•In response to the bus request the controller sends a
bus grant if the bus is free.
•The bus grant signal serially propagates through each
DAISY master until it encounters the first one that is
requesting access to the bus. This master blocks the
CHAININ propagation of the bus grant signal, activates the busy
line and gains control of the bus.

G •Therefore, any other requesting module will not

receive the grant signal and hence cannot get the bus
METHOD access.
DAISY CHAINING METHOD
Characteristics Description

Advantages 1. Simplicity and Scalability.

2. The user can add more devices anywhere along
the chain, up to a certain maximum value.

Disadvantages 1. The value of priority assigned to a device depends

on the position of master bus
2. Propagation delay arises in this method.
3. If one device fails then entire system will stop
working.
 •The system connections for polling method are shown
in figure below.
•In this the controller is used to generate the addresses
for the master. Number of address line required
depends on the number of devices connected in the
system.
•For example, if there are 8 devices connected in the
system, at least three address lines are required.

POLLING •In response to the bus request, controller generates a

sequence of master address. When the requesting
METHOD device recognizes its address, it activated the busy
line and begins to use the bus.
POLLING METHOD
Characteristics Description

Advantages 1. This method does not favor any particular device

and processor.
2. The method is also quite simple.
3. If one device fails, then entire system will not stop
working.
Disadvantages 1. Adding bus devices is difficult as increases the
number of address lines of the circuit.
 •This method is also called as Fixed Priority
method.
•The figure below shows the system connections
for the independent request scheme.

INDEPEN •In this scheme each master has a separate pair

of bus request and bus grant lines and each pair
DENT has a priority assigned to it.
•The built-in priority decoder within the controller
REQUEST selects the highest priority request and asserts
the corresponding bus grant signal.
METHOD
INDEPENDENT REQUEST
METHOD
Characteristics Description
Advantages 1. This method generates fast response.
Disadvantages 1. Hardware cost is high as large no. of control lines
are required.
 •In distributed arbitration, all devices participate in
the selection of the next bus master.
•In this scheme each device on the bus is assigned a
4-bit identification number.
•The number of devices connected on the bus when
one or more devices request for the control of bus,

DISTRIBU they assert the start-arbitration signal and place

their 4-bit ID numbers on arbitration lines, ARB0

TED through ARB3.

•These four arbitration lines are all open-collector.
ARBITRAT Therefore, more than one device can place their 4-
bit ID number to indicate that they need to control
ION of bus.
•When two or more devices place their ID number on
bus lines then it is necessary to identify the highest
ID number.
•The priority of the device will be determined by the
generated ID.
•LOGICAL OR Operation is performed for
Comparison.
DISTRIBUTED ARBITRATION
  Register Memory is
the smallest and fastest
memory in computer
system.
 It is not a part of the
main memory.
 It is located in the CPU
in form of registers,
which are the smallest
data holding elements.
 A register temporarily
holds frequently used
data, instructions, and
memory address that
REGISTER are to be used by CPU.
MULTIPLEXER
 Also called as Mux.
 It is a combinational circuit,
that has maximum 2^n data
inputs, n selection lines and
single output line.

Y=S1’S0’I0+S1’S0I1+S1SO’I2+
S1S0I3
TRI STATE
BUFFER
 Buffer is a logic circuit which amplifies
the current or voltage. It has one input
line and one output line.
In an ordinary logic circuit, there are
two output states: High(1) or Low(0).
 Complicated digital systems like
microprocessors, computers have the
output of multiple logic gates
connected to a common line (bus).
 In these complicated systems,
problem arise while transferring the
data. To avoid such problems, an extra
output state is included which is
termed as high impedance state.
 Such circuits with three output
states are called as Tri state circuits
have three terminals: input, output,
and control.
TRI STATE BUFFER
 DECODER
The combinational circuit that change the
binary information into 2N output lines is
known as Decoders.
 The binary information is passed in the
form of N input lines. The output lines
define the 2N-bit code for the binary
information.
 In simple words, the Decoder performs
the reverse operation of the Encoder. At a
time, only one input line is activated for
simplicity.
 The produced 2N-bit output code is
equivalent to the binary information.
 ENCODER
 The combinational circuits that change the
binary information into N output lines are
known as Encoders.
 The binary information is passed in the
form of 2N input lines.
 The output lines define the N-bit code for
the binary information.
 In simple words, the Encoder performs the
reverse operation of the Decoder.
 At a time, only one input line is activated
for simplicity. The produced N-bit output
code is equivalent to the binary information.
BUS AND MEMORY
TRANSFER
A digital system composed of many registers, and paths must be
provided to transfer information from one register to another.
The number of wires connecting all of the registers will be
excessive if separate lines are used between each register and all
other registers in the system.
A bus structure, on the other hand, is more efficient for transferring
information between registers in a multi-register configuration
system.
A bus consists of a set of common lines, one for each bit of register,
through which binary information is transferred one at a time.
Control signals determine which register is selected by the bus
during a particular register transfer.
BUS AND MEMORY
TRANSFER
USING MULTIPLEXER
The following block diagram shows a Bus system for
four registers.
It is constructed with the help of four 4 * 1 Multiplexers
each having four data inputs (0 through 3)
and two selection inputs (S1 and S2).
 BUS AND
MEMORY
TRANSFER USING
MULTIPLEXER
The two selection lines S1 and S2 are connected to
the selection inputs of all four multiplexers.
The selection lines choose the four bits of one
register and transfer them into the four-line common
bus.
When both of the select lines are at low logic, i.e.
S1S0 = 00, the 0 data inputs of all four multiplexers
are selected and applied to the outputs that forms
the bus.
This, in turn, causes the bus lines to receive the
content of register A since the outputs of this
register are connected to the 0 data inputs of the
multiplexers.
Similarly, when S1S0 = 01, register B is selected,
and the bus lines will receive the content provided by
register B.
The following function table shows the register that
is selected by the bus for each of the four possible
binary values of the Selection lines.
BUS AND MEMORY
TRANSFER USING THREE
STATE GATES (TRI-STATE
GATES)
A bus system can also be constructed using three-state
gates instead of multiplexers.
The three state gates can be considered as a digital circuit that
has three gates, two of which are signals equivalent to logic 1 and
0 as in a conventional gate. However, the third gate exhibits a high-
impedance state.
The most commonly used three state gates in case of the bus
system is a buffer gate.
The graphical symbol of a three-state buffer gate can be
represented as:
BUS AND MEMORY TRANSFER
USING THREE STATE GATES
(TRI-STATE GATES)
The following diagram demonstrates the construction of a bus
system with three-state buffers.
•The outputs generated by the
four buffers are connected to form
a single bus line.
•Only one buffer can be in active
state at a given point of time.
•The control inputs to the buffers
determine which of the four
normal inputs will communicate
with the bus line.
•A 2 * 4 decoder ensures that no
more than one control input is
active at any given point of time.
BUS AND MEMORY TRANSFER
*MEMORY TRANSFER*
• The transfer of information from a memory unit to the user end is called
a Read operation.
• The transfer of new information to be stored in the memory is called a Write operation.
• A memory word is designated by the letter M.
• We must specify the address of memory word while writing the memory transfer
operations.
• The address register is designated by AR and the data register by DR.
• Thus, a read operation can be stated as: Read: DR ← M [AR]
• The Read statement causes a transfer of information into the data register (DR) from the
memory word (M) selected by the address register (AR).
• And the corresponding write operation can be stated as: Write: M [AR] ← R1
• The Write statement causes a transfer of information from register R1 into the memory
word (M) selected by address register (AR).