Unit-2

Basic Electrical Properties

Unit-2 (part a)

 Basic Electrical Properties of MOS and BiCMOS circuits

 Ids-Vds relationships
 MOS transistor threshold voltage
 gm
 gds
 Figure of Merit (w0 )
 Zpu / Zpd
 Latch Up in CMOS
 Pass Transistors
Unit-2 (part b)
 NMOS Inverter

 Various Pull ups

 CMOS Inverter Analysis and Design

 Bi-CMOS Inverters
MOS Characteristics
 MOS – majority carrier device
 Carriers: e-- in nMOS, holes in pMOS
 Vt – channel threshold voltage
(cuts off for voltages < Vt)
Materials and Dopants

 SiO2 – low loss, high dielectric strength

 n type impurities: P, As, Sb
 p type impurities: B, Al, Ga
MOSFET Transistors

MOSFET – For given Vds & Vgs,

Ids controlled by:
 Distance between source & drain L
 Channel width W
 Threshold voltage Vt polysilicon
gate
 Gate oxide thickness tox W
tox

 Permittivity of SiO2 
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.9)
OX p-type body

 Carrier mobility 
nMOS Cutoff
 No channel
 Ids = 0
Vgs = 0 Vgd
+ g +
- -
s d
n+ n+

p-type body
b
nMOS Linear
 Channel forms
Vgs > Vt
 Current flows from d to s + g +
Vgd = Vgs

- -
s d
 e- from s to d Vds = 0
n+ n+

 Ids increases with Vds p-type body

b

 Similar to linear resistor

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b
nMOS Saturation
 Channel pinches off
 Ids independent of Vds
 We say current saturates
 Similar to current source
Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b
Drain to source current Ids Vs Voltage
Vds relationships

 The whole concept of the MOS transistor evolves from

the use of a voltage on the gate to induce a charge (Qc)

in the channel between source and drain, which may
then be caused to move from source to drain under the
influence of an electric field created by voltage Vds
applied between drain and source.
 Since charge induced is dependent on the gate to source

voltage Vgs, then Ids is dependent on both Vgs and Vds.

 Drain to source current Ids Vs Voltage
Vds relationships
 Ids= -Isd =
Charge induced in channel (Qc)/ Electron transit time(  )

Where transit time

 sd =Length of the channel (L)/Velocity(v)

But velocity v=µEds ( where µ=electron hole mobility and

Eds= electric field (drain to source) )

Vds L2
v  sd 
L Vds
The Non saturated region
 Charge induced in channel due to gate voltage is due to
the voltage difference between the gate and the channel.
 The voltage along the channel varies linearly with distance
x from the source due to the IR drop in the channel and
assuming that the device is not saturated then the average
value is Vds/2.

 The effective gate voltage Vg=Vgs-Vt where Vt is the

threshold voltage needed to invert the charge under the
gate and establish the channel.
The Non saturated region
 Charge per unit area = E  
g ins o

 Induced Charge, Qc E g  ins oWL

Where Eg is average electric field gate to channel
 ins = relative permittivity of insulation between gate and channel

o = permittivity of free space

 Vgs  Vt  Vds / 2 
E g   Where D is
 D  oxide thickness
 MOS transistor Threshold voltage Vt
 The gate structure of a MOS transistor consists, of charges
stored in the dielectric layers and in the surface to surface
interfaces as well as in the substrate itself.
 Switching an enhancement mode MOS transistor from the off to
the on state consists in applying sufficient gate voltage to
neutralize these charges and enable the underlying silicon to
undergo an inversion due to the electric field from the gate.
 Switching a depletion mode NMOS transistor from the on to the
off state consists of applying enough voltage to the gate to add
to the stored charge and invert the n implant region to p.
 The Threshold voltage Vt

QB  Qss
Vt  ms  2 fN
Co
QB is the charge per unit area in the depletion layer beneath the
oxide
QSS charge density at Si:SiO2 interface
Co is the capacitance per unit area
Φms is work function difference between gate and Si.
ΦfN is Fermilevel potential between inverted surface and bulk Si.
The Threshold voltage Vt
QB  2 o si qN (2 fN  VSB )columb/m2
Qss (1.5to8) x10  8 columb/m2
øfN = (kT/q) ln (N/ni ) volts
The Threshold voltage Vt - Body Effect

 Increasing VSB causes the channel to be depleted of charge

carriers and thus the threshold voltage is raised.

 Change in Vt is given by
V  (V )1 / 2
t SB
where  is a constant which depends on substrate
doping so that the more lightly doped the substrate,
the smaller will be the body effect.
MOS transistor figure of merit ω0

An indication of frequency response may be obtained from

the parameter ω0 where

gm   1 
0   2 Vgs  Vt   
Cg L   sd 
A fast circuit requires that gm be as high as possible.
 Latch Up in CMOS
 Latch-up is a condition in which the parasitic components
give rise to the establishment of low-resistance conducting
paths between VDD and VSS disastrous results.

 Latch up may be induced by glitches on the supply rails or

by incident radiation.
 There are two resistances and two transistors which form a

path between VDD and VSS .

Latch Up in CMOS

Latch-up effect in p-well structure

Latch Up in CMOS
 If sufficient substrate current flows to generate enough

voltage across Rs to turn on transistor T1 , this will then

draw current through Rp and, if the voltage developed is

sufficient, T2 will also turn on, establishing a self-

sustaining low-resistance path between the supply rails.

 If the current gains of the two transistors are such that β1

*β2 >1, latch up may occur.

 Latch Up in CMOS
 With no injected current, the
parasitic transistors will exhibit
high resistance, but sufficient
substrate current flow will
cause switching to the low-
resistance state.
 Once latched up, this condition
will be maintained until the Latch-up circuit model

latch up current drops below Il .

 Latch Up in CMOS
 It is thus essential for a CMOS process to ensure that Vl and

Il are not readily achieved in any normal mode of operation.

Latch-up effect in n-well structure

Latch Up in CMOS (Remedies)
 An increase in substrate doping levels with a consequent

drop in the value of Rs .

 Reducing Rp by control of fabrication parameters and by

ensuring a low contact resistance to VSS .

 Other more elaborate measures such as introduction of

guard rings.
PASS Transistors
 The isolated nature of the gate allows MOS transistors to
be used as switches in series with lines carrying logic
levels in a way that is similar to the use of relay
contacts.
 This application of the MOS device is called the Pass
transistor and switching logic arrays can be formed.
Inverter

Inverter : A basic requirement for producing a complete

range of Logic circuits.

This is needed for restoring logic levels for NAND and

NOR gates, and for sequential and memory circuits of
various formats.
1 0

0 1
 Vdd Basic Inverter: Transistor with source
connected to ground and a load resistor
connected from the drain to the positive
R Pull-Up Supply rail.
Vo Output is taken from the drain and the
input applied between gate and ground.
Vin
Resistors are not easily formed on silicon
Pull-Down - they occupy too much area
Vss Transistors can be used as the pull-up
device .
NMOS Inverter
Vdd

Pull-Up
With no current drawn from
Vout outputs, Ids for both transistors is
equal
Vin
Pull-Down

Vss
NMOS inverter transfer characteristic

As Vin exceeds the p.d

threshold voltage
current begins to flow.
The output voltage Vout
thus decreases and the
subsequent increases
in Vin will cause the
p.d. transistor to come
out of saturation and
become resistive.
Various Pull-Ups
 Load resistance RL: This
arrangement is not often
used because of the large
space requirements of
resistors produced in a
silicon substrate.
NMOS Depletion Mode Transistor pull
up and transfer Characteristics
NMOS Depletion Mode Transistor pull
up and transfer Characteristics

 Dissipation is high since rail to rail current flows when Vin

= Logical 1.
 Switching of Output from 1 to 0 begins when Vin exceeds
Vt of pull down device.
 When switching the output from 1 to 0, the pull up device
is non-saturated initially and this presents a lower
resistance through which to charge capacitive loads(Vds <
Vgs – Vt).
NMOS Enhancement Mode Transistor Pull - Up
NMOS Enhancement Mode Transistor Pull - Up

 Dissipation is high since current flows when Vin = 1

 Vout can never reach VDD (effect of channel)

 VGG can be derived from a switching source (i.e. one

phase of a clock, so that dissipation can be

significantly reduced.
 If VGG is higher than VDD, then an extra supply rail is

required.
 Complimentary Transistor Pull – Up (CMOS)

Vdd Vout Vtn Vtp

P on N on
Vin N off P off
Vo Both On

Vin

Vss Vss Vdd

Logic 0 Logic 1
 1: Logic 0 : p on ; n off

5: Logic 1: p off ; n on

I 2: Vin > Vtn.

Vdsn large – n in saturation
1 2 3 4 5 Vdsp small – p in resistive
Small current from Vdd to Vss

Vin 4: same as 2 except reversed p and n

3: Both transistors are in saturation

Large instantaneous current flows