UNIT-2

REGISTER
TRANSFER AND
MICROOPRATIONS
TOPICS
REGISTER TRANSFER LANGUAGE
REGISTER TRANSFER
BUS AND MEMORY TRANSFERS
ARITHMETIC MICRO OPERATIONS
LOGIC MICRO OPERATIONS
SHIFT MICRO OPERATIONS
ARITHMETIC LOGIC SHIFT UNIT
RESGISTER TRANSFER LANGUAGE
The symbolic notation
used to describe the micro
operation transfers among
registers is called a
register transfer language.
What is micro
operation?
 The operations executed
on data stored in registers
are called micro
operations.
Examples of micro
operations are shift, count,
clear and load.
RESGISTER TRANSFER
LANGUAGE
The term “register transfer”
implies the availability of
hardware logic circuits that can
perform a stated micro operation
and transfer the result of the
operation to the same or another
register.
The word “language” is borrowed
from programmers, who apply to
this term to programming
languages.
RESGISTER TRANSFER LANGUAGE
A register transfer language is a
system for expressing in symbolic
form the micro operation
sequences among the registers of
a digital module.
It is a convenient tool for
describing the internal
organization of digital computers.
It is believed to be as simple as
possible.
REGISTER TRANSFER
Computer registers are designated by
capital letters(sometimes followed by
numerals) to denote the function of the
register.
Example:
Register that holds address of memory unit
known as Memory Address Register
represented by MAR, (Program Counter)
PC, (Instruction Register) IR.
The most common way to represent a
register is by a rectangular box with the
name of the register inside.
REGISTER TRANSFER
REGISTER TRANSFER
 Information transfer from one register to
another is designated in symbolic form by
means of a replacement operator.
 R2R1
 R1-source register
 R2-destination register
 The statement denotes a transfer of the
content of register R1 into register R2.
 It designates a replacement of the content of
R2 by the content of R1.
 The content of the source register R1 does
not change after the transfer.
REGISTER TRANSFER
Normally, we want the transfer to occur
only under a predetermined control
condition. This can be shown by means of
an if-then statement.

 If(P==1)then(R2R1)
where P is a control signal generated in
the control section.
It is sometimes convenient to separate
the control variables from the register
transfer operation by specifying a control
function.
REGISTER TRANSFER
A control function is a Boolean
variable that is equal to 1 or 0.
The control function is included in
the statement as follows:
 P: R2  R1
The control condition is
terminated with a colon. It
symbolizes the requirement that
the transfer operation be
executed by the hardware only if
 REGISTER TRANSFER
Figure 4-2 shows the block diagram that
depicts the transfer from R1 to R2.
The n outputs of register R1 are connected to
the n inputs of register R2.
The letter n will be used to indicate any
number of bits for the register. It will be
replaced by an actual number when the
length of the register is known.
Register R2 has a load input that is activated
by the control variable P.
It is assumed that the control variable is
synchronized with the same clock as the one
applied to the register.
REGISTER TRANSFER
EXPLANATION
 As shown in the timing diagram, P is activated in
the control section by the rising edge of a clock
pulse at time t.
 The next positive transition of the clock at time t
+ 1 finds the load input active and the data inputs
of R2 are then loaded into the register in parallel.
 P may go back to 0 at time t + 1; otherwise, the
transfer will occur with every clock pulse transition
while P remains active.
 It is assumed that all transfers occur during a clock
edge transition.
 The actual transfer does not occur until the register is
triggered by the next positive transition of the clock at
time t + 1.
REGISTER TRANSFER
BUS AND MEMORY TRANSFERS

What is a bus?
A bus structure consists of a set of
common lines, one for each bit of a
register, through which binary
information is transferred one at a
time.
Control signals determine which
register is selected by the bus
during each particular register
transfer.
Why do we need bus?
A typical digital computer has many
registers, and paths must be provided
to transfer information from one
register to another.
The number of wires will be excessive if
separate lines are used between each
register and all other registers in the
system.
A more efficient scheme for transferring
information between registers in a
multiple-register configuration is a
common bus system.
BUS AND MEMORY TRANSFERS
EXPLANATION
 One way of constructing a common bus system is with
multiplexers.
 The multiplexers select the source register whose binary
information is then placed on the bus. The construction of a
bus system for four registers is shown in Fig. 4-3.
 Each register has four bits, numbered 0 through 3. The bus
consists of four 4 x 1 multiplexers each having four data
inputs, 0 through 3, and two selection inputs, S1 and S0.
 In order not to complicate the diagram with 16 lines
crossing each other, we use labels to show the connections
from the outputs of the registers to the inputs of the
multiplexers. For example, output 1 of register A is
connected to input 0 of MUX 1 because this input is
labelled A1.
 The diagram shows that the bits in the same significant
position in each register are connected to the data inputs
of one multiplexer to form one line of the bus. Thus MUX 0
multiplexes the four 0 bits of the registers, MUX 1
multiplexes the four 1 bits of the registers, and similarly for
the other two bits.
The two selection lines S1 and S0 are
connected to the selection inputs of all four
multiplexers.
The selection lines choose the four bits of one
register and transfer them into the four-line
common bus.
When S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the
outputs that form the bus. This causes the bus
lines to receive the content of register A since
the outputs of this register are connected to
the 0 data inputs of the multiplexers.
Similarly, register B is selected if S1S0 = 01,
and so on.
Table 4-2 shows the register that is selected
by the bus for each of the four possible binary
value of the selection lines.
BUS AND MEMORY TRANSFERS
BUS AND MEMORY TRANSFERS
For example, a common bus
for eight registers of 16 bits
each requires 16 multiplexers,
one for each line in the bus.
Each multiplexer must have
eight data input lines and
three selection lines to
multiplex one significant bit in
the eight registers.
The symbolic statement for a bus
transfer may mention the bus or its
presence may be implied in the
statement. When the bus is included in
the statement, the register transfer is
symbolized as follows:
 BUS  C, R1  BUS
The content of register C is placed on the
bus, and the content of the bus is loaded
into register R 1 by activating its load
control input. If the bus is known to exist
in the system, it may be convenient just
to show the direct transfer.
 R1  C
THREE-STATE BUS BUFFERS
A bus system can be constructed with three-state
gates instead of multiplexers.
 A three-state gate is a digital circuit that exhibits
three states. Two of the states are signals
equivalent to logic 1 and 0 as in a conventional
gate. The third state is a high-impedance state.
 Logic-0 is a fixed voltage value.
 Logic-1 signal can be generated through an inverter
whose input is 0.
 The high-impedance state behaves like an open
circuit, which means that the output is
disconnected and does not have a logic
significance.
 Three-state gates may perform any conventional
logic, such as AND or NAND. However, the one most
commonly used in the design of a bus system is the
buffer gate.
EXPLANATION
 The graphic symbol of a three-state buffer gate is
shown in Fig. 4-4. It is distinguished from a normal
buffer by having both a normal input and a
control input.
 The control input determines the output state.
When the control input is equal to 1, the output is
enabled and the gate behaves like any
conventional buffer, with the output equal to the
normal input.
 When the control input is 0, the output is
disabled and the gate goes to a high-impedance
state, regardless of the value in the normal input.
 The high-impedance state of a three-state gate
provides a special feature i.e. a large number of
three-state gate outputs can be connected with
wires to form a common bus line without
endangering loading effects.
EXPLANATION
The construction of a bus system with
three-state buffers is demonstrated in Fig.
4-5.
The outputs of four buffers are connected
together to form a single bus line.
The control inputs to the buffers determine
which of the four normal inputs will
communicate with the bus line .
 No more than one buffer may be in the
active state at any given time. The
connected buffers must be controlled so
that only one three-state buffer has access
to the bus line while all other buffers are
maintained in a high impedance state.
One way to ensure that no more than
one control input is active at any
given time is to use a decoder, as
shown in the diagram.
When the enable input of the decoder
is 0, all of its four outputs are 0, and
the bus line is in a high-impedance
state because all four buffers are
disabled.
When the enable input is active, one
of the three-state buffers will be
active, depending on the binary value
in the select inputs of the decoder.
MEMORY TRANSFERS
 The transfer of information from a memory
word to the outside environment is called a
read operation.
 The transfer of new information to be stored
into the memory is called a write operation.
 A memory word will be symbolized by the letter
M. The particular memory word among the
many available is selected by the memory
address during the transfer.
 It is necessary to specify the address of M when
writing memory transfer operations.
 This will be done by enclosing the address in
square brackets following the letter M.
MEMORY TRANSFERS
Consider a memory unit that receives
the address from a register, called the
address register, symbolized by AR .
The data are transferred to another
register, called the data register,
symbolized by DR . The read operation
can be stated as follows:
 Read: DR  M[AR]
This causes a transfer of information
into DR from the memory word M
selected by the address in AR.
MEMORY TRANSFERS
The write operation transfers the
content of a data register to a
memory word M selected by the
address. Assume that the input
data are in register Rl and the
address is in AR.
Write : M[AR]R1
This causes a transfer of
information from R1 into the
memory word M selected by the
 MICROOPERATIONS
A micro operation is an elementary
operation performed with the data
stored in registers.
They are classified into 4
categories.
1)Register transfer micro
operations transfer binary
information from one register to
another.
Example: R2R1
 MICROOPERATIONS
2) Arithmetic micro operations
perform arithmetic operation on
numeric data stored in registers.
3)Logic micro operations perform
bit manipulation operations on
non numeric data stored in
registers.
 4)Shift micro operations perform
shift operations on data stored in
registers.
ARITHMETIC MICROOPERATIONS
The basic arithmetic micro
operations are addition,
subtraction, increment,
decrement and shift.
ADD OPERATION
 R3R1+R2
It states that contents of register
R1 are added to the contents of
register R2 and the sum
transferred to the register R3.
SUBTRACTION MICROOPERATION
Itcan be implemented in 2 ways
 R3R1+R2 +1
 (or)
 R3R1-R2
R2 is the 1’s complement of R2.
Adding 1 to the 1’s complement
produces the 2’s complement.
Therefore adding 2’s complement
to R1 is equivalent to R1-R2.
The arithmetic operations of multiply and
divide are not listed in Table 4- 3.
 These two operations are valid arithmetic
operations but are not included in the basic
set of micro operations.
 The only place where these operations can
be considered as micro operations is in a
digital system, where they are implemented
by means of a combinational circuit.
In most computers, the multiplication
operation is implemented with a sequence
of add and shift micro operations.
Division is implemented with a sequence of
subtract and shift micro operations.
BINARY ADDER
To implement the add micro
operation with hardware, we need
the registers that hold the data
and the digital component that
performs the arithmetic addition.
The digital circuit that forms the
arithmetic sum of two bits and a
previous carry is called a full-
adder.
The digital circuit that generates
the arithmetic sum of two binary
 BINARY ADDER
An n-bit binary adder requires n full-
adders.
The output carry from each full-adder is
connected to the input carry of the next-
high-order full-adder.
The n data bits for the A inputs come
from one register (such as R1), and the n
data bits for the B inputs come from
another register (such as R2).
The sum can be transferred to a third
register or to one of the source registers
(R 1 or R2), replacing its previous content.
EXAMPLE : 4 BIT BINARY ADDER
EXPLANATION
The binary adder is constructed with full-
adder circuits connected in cascade,
with the output carry from one full-adder
connected to the input carry of the next
full-adder.
Figure 4-6 shows the interconnections of
four full-adders (FA) to provide a 4-bit
binary adder.
The augend bits of A and the addend
bits of B are designated by subscript
numbers from right to left, with subscript
0 denoting the low-order bit.
The carries are connected in a
chain through the full-adders.
 The input carry to the binary
adder is C0
The output carry is C.
The S outputs of the full-adders
generate the required sum bits.
 BINARY ADDER-
SUBTRACTOR
As discussed earlier subtraction A
- B can be done by taking the 2's
complement of B and adding it to
A.
The 2's complement can be
obtained by taking the 1' s
complement and adding one to the
least significant pair of bits.
The 1's complement can be
implemented with inverters and a
one can be added to the sum
4-BIT BINARY ADDER-
SUBTRACTOR
EXPLANATION
The addition and subtraction
operations can be combined into one
common circuit by including an
exclusive-OR gate with each full-
adder.
A 4-bit adder-subtractor circuit is
shown in Fig. 4-7. The mode input M
controls the operation.
When M = 0 the circuit is an adder.
When M = 1 the circuit becomes a
subtractor.
 - Symbol for exclusive-OR
Each exclusive-OR gate receives input M
and one of the inputs of B. When M = 0, we
have B 0 = B. The full-adders receive the
value of B, the input carry is O, and the
circuit performs A plus B. When M = 1, we
have B 1 = B' and C0 = 1.
The B inputs are all complemented and a 1
is added through the input carry.
The circuit performs the operation A plus
the 2's complement of B.
For unsigned numbers, this gives A - B if
A >= B or the 2's complement of (B - A) if A
< B.
 For signed numbers, the result is A - B
provided that there is no overflow.
 BINARY INCREMENTER
The increment micro operation
adds one to a number in a register.
For example, if a 4-bit register has
a binary value 0110, it will go to
01I I after it is incremented. This
micro operation is easily
implemented with a binary counter
.
BINARY INCREMENTER
Every time the count enable is
active, the clock pulse transition
increments the content of the
register by one.
There may be occasions when
the increment micro operation
must be done with a
combinational circuit
independent of a particular
register.

EXPLANATION
The diagram of a 4-bit combinational circuit
incrementer is shown in Fig. 4-8.
One of the inputs to the least significant
half-adder (HA) is connected to logic-1 and the
other input is connected to the least significant
bit of the number to be incremented.
The output carry from one half-adder is
connected to one of the inputs of the next-
higher-order half-adder.
The circuit receives the four bits from A0,
through A3, adds one to it, and generates the
incremented output in S0 through S3.
The output carry C4, will be 1 only after
incrementing binary 1111. This also causes
outputs S0 through S3, to go to 0.
ARITHMETIC CIRCUIT
The basic component of an
arithmetic circuit is the parallel
adder. By controlling the data
inputs to the adder, it is possible to
obtain different types of arithmetic
operations.
EXAMPLE: 4-bit arithmetic circuit
EXPLANATION
Ithas 4 full adder circuits that constitute
the 4bit adder and 4 multiplexers for
choosing different operations.
There are two 4-bit inputs A and B and
a 4-bit output D.
The 4 inputs from A go directly to the X
inputs of the binary adder.
Each of the 4 inputs from B are
connected to the data inputs of the
multiplexers.
The multiplexers data inputs also
receive the complement of B.
The other 2 data inputs are
connected to logic-0 and logic-1.
Logic-0 is a fixed voltage value.
Logic-1 signal can be generated
through an inverter whose input is 0.
The 4 multiplexers are controlled by
2 selection inputs, S1 and S0.
The input carry Cin goes to the carry
input of the full adder in the least
significant position.
The other carries are connected from
one stage to the next.
The output of the binary adder is
calculated from the following
arithmetic sum:
 D = A + Y + Cin
A is 4-bit binary number at X inputs
Y is 4-bit binary number at Y inputs of
binary adder
Cin is the input carry, which can be
equal to 1 or 0.
+ denotes arithmetic plus
By controlling Y with 2 selection lines
S1 and S0 and making Cin equal to 0
or 1 there are 8 possible arithmetic
micro operations which are discussed
The 8 possible operation are
explained as follows :
ADDITION :
When S1S0 = 00, the value of B is
applied to the Y inputs of the
adder.
If Cin = 0, the output is
 D=A+B
If Cin = 1, the output is
 D=A+B+1
Both cases perform addition
operation
SUBTRACTION :
When S1S0 = 01, the complement
of B is applied to the Y inputs of
the adder.
If Cin = 1, then
 D=A+B+1
This produces A plus the 2’s
complement
 of B, which is equal to A-B.
If Cin = 0, then
 D=A+B
Which is equivalent to A-B-1
INCREMENT :
When S1S0 = 10, the inputs from B
are neglected, and instead, all 0’s
are inserted into the Y inputs.
The output becomes
 D = A + 0 + Cin
If Cin = 0
 D=A
Here we have a direct transfer from
input A to output D
If Cin = 1
 D=A+1
Here value of A is incremented by 1
DECREMENT :
When S1S0 = 11, all 1’s are inserted
into the Y inputs of the adder to produce
the decrement operation.
If Cin = 0, the output is
 D=A–1
This is because a number with all 1’s is
equal to the 2’s complement of 1.
Adding a number A to the 2’s
complement of 1 produces
 F = A + 2’s complement of 1
 => F = A – 1
If Cin = 1, the output is
 D=A–1+1

LOGIC MICROOPERATIONS
Logic microoperations specify binary operations
for strings of bits stored in registers.
These operations consider each bit of the
register separately and treat them as binary
variables.
For example, the exclusive-OR microoperation
with the contents of two registers R 1 and R2 is
symbolized by the statement.
 P: R1  R1 R2
It specifies a logic microoperation to be executed
on the individual bits of the registers provided
that the control variable P = 1.
 As a numerical example, assume that each
register has four bits. Let the content of R1 be
1010 and the content of R2 be 1100.
The exclusive-OR microoperation stated
above symbolizes the following logic
computation:
 1010 Content of R1
 1100 Content of R2
 0110 Content of R1 after P = 1
The content of R1, after the execution of
the microoperation, is equal to the bit-by-
bit exclusive-OR operation on pairs of bits
in R2 and previous values of Rl.
The logic microoperations are seldom used
in scientific computations, but they are
very useful for bit manipulation of binary
data and for making logical decisions.
SPECIAL SYMBOLS
 Special symbols will be adopted for the logic
microoperations OR, AND, and complement, to
distinguish them from the corresponding
symbols used to express Boolean functions.
 The symbol V will be used to denote an OR
microoperation and the symbol /\ to denote an
AND microoperation.
 By using different symbols, it will be possible
to differentiate between a logic microoperation
and a control (or Boolean) function.
 The + symbol has two meanings, it will be
possible to distinguish between them by noting
where the symbol occurs.
 When the symbol + occurs in a microoperation,
it will denote an arithmetic plus.
 When it occurs in a control (or Boolean)
function, it will denote an OR operation.
 We will never use it to symbolize an OR
microoperation.
 For example, in the statement.
 P + Q: R1  R2 + R3, R4  R5 V R6
 the + between P and Q is an OR operation
between two binary variables of a control
function.
 The + between R2 and R3 specifies an add
microoperation.
 The OR microoperation is designated by the
symbol V between registers R5 and R6.
LIST OF LOGIC OPERATIONS
There are 16 different logic operations
that can be performed with two binary
variables.
They can be determined from all
possible truth tables obtained with two
binary variables as shown in Table 4-5.
In this table, each of the 16 columns F0
through F15 represents a truth table of
one possible Boolean function for
the two variables x and y.
Note that the functions are determined
from the 16 binary combinations that
can be assigned to F.
HARDWARE IMPLEMENTATION
The hardware implementation of
logic micro operations requires that
logic gates be inserted for each bit
or pair in the registers to perform
the required logic function.
Figure 4-10 One stage of logic
circuit
The above diagram consists of 4 gates
and a multiplexer.
Each of the 4 logic operations is generated
through a gate that performs the required
logic.
The outputs of the gates are applied to the
data inputs of the multiplexer and direct
its value to the output.
The diagram shows one typical stage with
script i.
For a logic circuit with n bits, the diagram
must be repeated n times for i=0,1,2,.,n-1.
The function table lists the logic micro
operations obtained for each combination
of the selection variables.
SOME APPLICATIONS
Logic micro operations are very useful for
manipulating individual bits or a portion of a
word stored in a register.
They can be used to change bit values,
delete a group of bits, or insert new bit
values into a register.
The following examples show how bits of one
register(designated by A) are manipulated by
logic micro operations as a function of the
bits of another register(designated by B).
In a typical application, register A is a
processor register and the bits of register B
constitute a logic operand extracted from
memory and placed in register B.
SELECTIVE-SET
 The selective-set operation sets to 1 the bits in register A
where there are corresponding 1's in register B. It does not
affect bit positions that have 0's in B. The following
numerical example clarifies this operation.
 1010 A before
 1100 B (logic operand)
 1110 A after
 The two leftmost bits of B are 1' s, so the corresponding
bits of A are set to 1. One of these two bits was already set
and the other has been changed from 0 to I.
 The two bits of A with corresponding 0' s in B remain
unchanged.
 The example above serves as a truth table since it has all
four possible combinations of two binary variables.
 From the truth table we note that the bits of A after the
operation are obtained from the logic-OR operation of bits
in B and previous values of A. Therefore, the OR micro
operation can be used to selectively set bits of a register.
 SELECTIVE-COMPLEMENT
 The selective-complement operation complements
bits in A where there are selective-clear
corresponding l's in B. It does not affect bit positions
that have 0's in B.
 For example
 1010 A before
 1100 B (logic operand)
 0110 A after
 Again the two leftmost bits of B are 1's, so the
corresponding bits of A are complemented.
 This example again can serve as a truth table from
which one can deduce that the selective-
complement operation is just an exclusive-OR Micro
operation.
 Therefore, the exclusive-OR micro operation can be
used to selectively complement bits of a register.
SELECTIVE-CLEAR
The selective-clear operation clears to 0
the bits in A only where there are
corresponding 1’s in B. For example:
 1010 A before
 1100 B(logic operand)
 0010 A after
Again the 2 leftmost bits of B are 1’s, so
the corresponding bits of A are cleared to
zero. One can deduce that the Boolean
operation performed on the individual bits
in AB.
The corresponding logic micro operation is
 A  A /\ B
MASK OPERATION
The mask operation is similar to the
selective-clear operation except that the bits
of A are cleared only where there are
corresponding 0’s in B.
The mask operation is an AND micro
operation.
Ex : 1010 A before
 1100 B(logic operand)
 1000 A after masking
The 2 rightmost bits of A are cleared
because the corresponding bits of B are 0’s.
The 2 leftmost bits are left unchanged
because the corresponding bits of B are 1’s.
INSERT OPERATION
 The insert operation inserts a new value into a
group of bits. This is done by first making the
bits and then ORing them with the required
value. For example, suppose that an A register
contain 8 bits, 0110 1010. To replace the 4
leftmost bits by the value 1001 we first mask
the 4 unwanted bits :
 0110 1010 A before
 0000 1111 B(mask)
 0000 1010 A after masking
and then insert the new value:
 0000 1010 A before
 1001 0000 B(insert)
 1001 1010 A after insertion
 The insert operation is an OR micro operation
CLEAR OPERATION
The clear operation compares the words in A
and B and produces an all 0’s result if the 2
numbers are equal. This operation is achieved
by an exclusive-OR micro operation as shown
by the following example:
 1010 A
 1010 B
 0000 A A B
When A and B are equal, the 2 corresponding
bits are either both 0 or both 1.
 In either case the exclusive-OR operation
produces a 0. The all 0’s result is then checked
to determine if the 2 numbers were equal.
SHIFT MICROOPERATION
 Shift micro operations are used for serial transfer of
data.
 They are also used in conjunction with arithmetic,
logic, and other data-processing operations.
 The contents of a register can be shifted to the left
or the right.
 At the same time that the bits are shifted, the first
flip-flop receives its binary information from the
serial input.
 During a shift-left operation the serial input
transfers a bit into the rightmost position.
 During a shift-right operation the serial input
transfers a bit into the leftmost position.
 The information transferred through the serial input
determines the type of shift.
 There are three types of shifts:
LOGICAL SHIFT
A logical shift is one that transfers 0 through the
serial input. We will adopt the symbols shl and
shr for logical shift-left and shift-right micro
operations.
 For example:
 R1 ← shl R1
 R2 ← shr R2
 are two micro operations that specify a 1-bit shift
to the left of the content of register R1 and a 1-
bit shift to the right of the content of register R2.
 The register symbol must be the same on both
sides of the arrow.
 The bit transferred to the end position through
the serial input is assumed to be 0 during a
logical shift.
CIRCULAR SHIFT
The circular shift (also known as
a rotate operation) circulates the
bits of the register around the two
ends without loss of information.
This is accomplished by connecting
the serial output of the shift
register to its serial input.
We will use the symbols cil and
cir for the circular shift left and
right, respectively.
The symbolic notation for the shift
ARITHMETIC SHIFT
An arithmetic shift is a Micro operation that shifts a
signed binary number to the left or right.
An arithmetic shift-left multiplies a signed binary
number by 2.
An arithmetic shift-right divides the number by 2.
Arithmetic shifts must leave the sign bit unchanged
because the sign of the number remains the same
when it is multiplied or divided by 2.
The leftmost bit in a register holds the sign bit, and the
remaining bits hold the number.
The sign bit is 0 for positive and 1 for negative.
Negative numbers are in 2's complement form.
Figure 4-11 shows a typical register of n
bits. Bit R n- 1 in the leftmost position holds
the sign bit.
Rn-2 is the most significant bit of the
number and Ro is the least significant bit.
The arithmetic shift-right leaves the sign
bit unchanged and shifts the number
(including the sign bit) to the right. Thus
Rn-1 remains the same, Rn-2 receives the bit
from Rn-1 and so on for the other bits in the
register. The bit in Ro is lost.
The arithmetic shift-left inserts a 0 into
R0 and shifts all other bits to the left. The
initial bit of Rn-1 is lost and replaced by the
bit from Rn-2.
A sign reversal occurs if the bit in Rn-1 changes in
value after the shift.
 This happens if the multiplication by 2 causes an
overflow.
 An overflow occurs after an arithmetic shift left if
initially, before the shift, Rn-1 is not equal to Rn-2.
 An overflow flip-flop Vs can be used to detect an
arithmetic shift-left overflow.
 Vs = Rn-1 Rn-2
 If Vs = 0, there is no overflow, but if Vs = I, there
is an overflow and a sign reversal after the shift.
 Vs must be transferred into the overflow flip-flop
with the same clock pulse that shifts the register.
HARDWARE IMPLEMENTATION
A possible choice for a shift unit would be a
bidirectional shift register with parallel load.
 Information can be transferred to the register in
parallel and then shifted to the right or left.
 In this type of configuration, a clock pulse is needed
for loading the data into the register, and another
pulse is needed to initiate the shift.
 In a processor unit with many registers it is more
efficient to implement the shift operation with a
combinational circuit.
 In this way the content of a register that has to be
shifted is first placed onto a common bus whose
output is connected to the combinational shifter, and
the shifted number is then loaded back into the
register. This requires only one clock pulse for
loading the shifted value into the register.
4-BIT COMBINATIONAL CIRCUIT SHIFTER
FIGURE 4-12
SHIFTER
The 4-bit shifter has four data inputs,
A0 through A3 and four data outputs,
H0 through H3.
There are two serial inputs, one for shift
left (IL) and the other for shift right (h).
When the selection input S = 0, the input data
are shifted right (down in the diagram).
When S = 1, the input data are shifted left (up
in the diagram).
The function table in Fig. 4-12 shows which
input goes to each output after the shift.
A shifter with n data inputs and outputs
requires n multiplexers. The two serial inputs
can be controlled by another multiplexer to
provide the three possible types of shifts.
ARITHMETIC LOGIC SHIFT UNIT
The ALU is a combinational circuit, so that the
entire register transfer operation from the
source registers through the ALU and into the
destination register can be performed during
one clock pulse period.
The shift micro operations are often overall in a
separate unit, but sometimes the shift unit is
made part of the overall ALU.
The arithmetic, logic, and shift circuits can be
combined into one ALU with common selection
variables.
One stage of an arithmetic logic shift unit is
shown in Fig. 4-13. The subscript i designates a
typical stage.
Inputs A1 and B1 are applied to both the
arithmetic and logic units.
A 4 x 1 multiplexer at the output
chooses between an arithmetic
output in Ei and a logic output in Hi.
The data in the multiplexer are
selected with inputs S3 and S2.
The other two data inputs to the
multiplexer receive inputs Ai - 1 for the
shift-right operation and Ai + 1 for the
shift-left operation.
The circuit of Fig. 4-13 must be
repeated n times for an n-bit ALU.
The output carry Ci + 1 of a given
arithmetic stage must be connected
to the input carry Ci of the next stage
The input carry to the first stage is
the input carry Cin, which provides a
selection variable for the arithmetic
operations.
The circuit whose one stage is
specified in Fig. 4-13 provides eight
arithmetic operation, four logic
operations, and two shift operations.
Each operation is selected with the
five variables S3, S2, S1, S0, and
Cin The input carry Cin is used for
selecting an arithmetic operation only.
Table 4-8 lists the 14 operations of
the ALU. The first eight are arithmetic
operations and are selected with
S3S2 = 00. The next four are logic
operations and are selected with
S3S2 = 01. The input carry has no
effect during the logic operations and
is marked with don't-care x's. The last
two operations are shift operations
and are selected with S3S2 = 10 and
11. The other three selection inputs
have no effect on the shift.