MICROPROJECT REPORT ON
Even Parity Generator
In Partial Fulfillment of Diploma in Electronics
And Telecommunication Engineering
(Fourth Semester)
In the Subject of Digital Communication
(EC3407)
By
1. Sarthak Pawar 22EC527
2. Piyush Digraskar 22EC528
3. Mahesh Rathod 22EC534
4. Harshal Raut 22EC535
5. Vaishnavi Raut 22EC537
6. Nikhil Sambare 22EC539
7. Vedant Saraf 22EC540
GOVERNMENT POLYTECHNIC,
AMRAVATI
An Autonomous Institute of Govt. Of
Maharashtra
Under the Guidance of
Prof. S. M. Kale
Lecturer in Electronics and Tele. Engineering
Department of Electronics and Tele.
Engineering
Government Polytechnic, Amravati
INDEX
1. Introduction
2. Resources Required
3. Circuit Diagram
4. Working And Construction
5. Actual Model
6. Advantages
7. Applications
8. Conclusion
INTRODUCTION
Parity Generator
It is combinational circuit that accepts an n-1 bit
data and generates the additional bit that is to be
transmitted with the bit stream. This additional or
extra bit is called as a Parity Bit.
In even parity bit scheme, the parity bit is ‘0’ if
there are even number of 1s in the data stream
and the parity bit is ‘1’ if there are odd number of
1s in the data stream.
In odd parity bit scheme, the parity bit is ‘1’ if there
are even number of 1s in the data stream and the
parity bit is ‘0’ if there are odd number of 1s in the
data stream. Let us discuss both even and odd
parity generators.
Even Parity Generator
Let us assume that a 3-bit message is to be
transmitted with an even parity bit. Let the three
inputs A, B and C are applied to the circuit and
output bit is the parity bit P. The total number of 1s
must be even, to generate the even parity bit P.
The figure below shows the truth table of even
parity generator in which 1 is placed as parity bit in
order to make all 1s as even when the number of
1s in the truth table is odd.
Resources Required
1. IC 7486 (EX-OR Gate IC)
2. 4 bit DIP switch
3. 9V DC battery
4. LEDs
5. Resistor (1kohm)
6. IC 7805 (Regulator IC- fixed 5V supply)
7. Connecting Wires
8. Breadboard
CIRCUIT DIAGRAM
WORKING AND CONSTRUCTION
Let us assume that a 3-bit message is to be
transmitted with an even parity bit. Let the three
inputs A, B and C are applied to the circuit and
output bit is the parity bit P. The total number of 1s
must be even, to generate the even parity bit P.
The figure below shows the truth table of even
parity generator in which 1 is placed as parity bit in
order to make all 1s as even when the number of 1s
in the truth table is odd.
The above expression can be implemented by using
two Ex-OR gates. The logic diagram of even parity
generator with two Ex – OR gates is shown below.
The three bit message along with the parity
generated by this circuit which is transmitted to the
receiving end where parity checker circuit checks
whether any error is present or not.
To generate the even parity bit for a 4-bit data,
three Ex-OR gates are required to add the 4-bits
and their sum will be the parity bit.
ACTUAL MODEL
ADVANTAGES
• Reliability: Parity generators and checkers
provide highly reliable data transmission,
ensuring data integrity and accuracy.
• · Simplicity: Their design is relatively simple,
making them easy to integrate into various
electronic systems.
• · Real-time: Parity checking can detect errors in
data transmission in real-time, correcting errors
promptly during data transmission.
APPLICATIONS
• One important application of the use of an
Exclusive-OR gate is to generate parity.
• Parity is used to detect errors in transmitted
data caused by noise or other disturbances.
• A parity bit is an extra bit that is added to a data
word and can be either odd or even parity.
CONCLUSION
Thus the parity generating/checking method is one
of the most widely used error detection techniques
for data transmission; a parity bit is appended to
the transmitted data to make the binary data's
sum of 1s either even or odd. This bit is used to
detect errors during the transmission of binary
data.