Logic Gates Using CMOS
Signal Strength
• Strength of signal
– How close it approximates ideal voltage source
• VDD and GND rails are strongest 1 and 0
• nMOS pass strong 0
– But degraded or weak 1
• pMOS pass strong 1
– But degraded or weak 0
• Thus nMOS are best for pull-down network
CMOS INVERTER
F = (A)’
LOGIC GATES
F = (v1.v2)’ F = (v1 + v2)’
STICK DIAGRAM
STICK Diagram
• Stick diagram are useful for planning the layout and
routing of integrated circuits.
• It act as an interface between symbolic circuits and
actual layout.
• It does show all components
• It does not show exact placement of components.
Layer Representation
The layers may be represented as:
A suitable color scheme
Varying shading or stipple patterns
Varying line styles
A combination of the above
Stick Diagram Color Code
Component Color Use
metal 1 Power and signal wires
metal 2 Power wires
polysilicon Signal wires and transistor
gates
Signal wires,source and drain
n-diffusion of transistors
Signal wires,source and drain
p-diffusion of transistors
Signal connection
contact
via Connection between
metals
Transistors
nNMOS Transistor
pMOS Transistor
INVERTER- STICK DIAGRAM
CMOS Inverter
NAND Gate
NOR Gate
Stick Diagram - Example II
Power
A Out
Ground
nMOS Inverter (Depletion mode )
5V 5v
Dep
Vout
Vin
Enh in
0V
0V
Points to Ponder
• be creative with layouts
• sketch designs first
• minimize junctions but avoid long poly runs
• have a floor plan plan for input, output, power
and ground locations
CMOS Latch up
• Latch up is a condition in which parasitic
components give rise to the establishment
of low resistance conducting path between
VDD and VSS.
• It is induced by glitches on the supply rails
or by incident radiation
• Q1, Q2 and R form the path between VDD
and VSS.
• Sufficient Isub flows to generate enough
voltage across Rsub to turn on Q2, this will
then draw ct thro Rwell and if sufficient
voltage is developed Q1 is on
• If ct gain of Q1 and Q2 greater than 1 latch
up ocuur