5.

Processor Organization
 Unit 5. Processor Organization
• Instruction Cycle- The indirect cycle and Data flow.
• Instruction Pipelining- Pipelining Strategy, pipeline
performance, pipeline hazards, dealing with branches,
• Case Study- Intel 586 pipelining.
• Instruction level parallelism and superscalar processors-
Super scalar verses super pipelined, constraints,
• Design Issues instruction level and machine parallelism,
• Instruction issue policy, register renaming, machine
parallelism, branch prediction, superscalar execution &
implementation.
• Case Study- Pentium 4
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 Instruction Cycle
A program that exists inside a computer's

memory unit consists of a series of instructions.

The processor executes these instructions

through a cycle for each instruction.

In a basic computer, each instruction cycle

consists of the following phases:

Instruction fetch: fetch instruction from

memory

Decode the instruction: what operation to be

performed.

Read the effective address from memory :

 Registers Involved In Instruction Cycle

Memory address registers(MAR) : It is connected to System Bus

address lines. It specifies the address of a read or write operation in

memory.

Memory Buffer Register(MBR) : It is connected to the data lines of the

system bus. : It is connected to the system bus Data Lines. It holds the

memory value to be stored, or the last value read from the memory.

Program Counter(PC) : Holds the address of the next instruction to be

fetched.
Instruction Cycle State Diagram
 Fetch cycle
The address of the next instruction to execute is in the Program Counter(PC) at the

beginning of the fetch cycle.

Step 1: The address in the program counter is transferred to the Memory Address

Register(MAR), as this is the only register that is connected to the system bus

address lines.

Step 2: The address in MAR is put on the address bus, now a Read order is

provided by the control unit on the control bus, and the result appears on the data

bus and is then copied into the memory buffer register. Program counter is

incremented by one, to get ready for the next instruction. These two acts can be

carried out concurrently to save time.

Step 3: The content of the MBR is moved to the instruction register(IR).

Instruction fetch cycle consist of four micro
operation
 Decode instruction cycle
The next move is to fetch source operands once an instruction is fetched.

Indirect addressing (it can be obtained by any addressing mode, here it is done

by indirect addressing) is obtained by Source Operand. You don't need to fetch

register-based operands. If the opcode is executed, it will require a similar

process to store the result in main memory. Micro operations take place:

Step 1: The instruction address field is passed to the MAR. This is used to

fetch the operand 's address.

Step 2: The address field of the IR is updated from the MBR.

 Execute instruction Cycle
The initial three cycles (Fetch, Indirect, and Interrupt) are predictable and quick. Each
requires simple , small, and fixed micro-operation sequences. The same micro-operation
is repeated every time around in each event. Execute instruction cycle is different from
them. Like, there is N different series of micro-operations that can occur for a computer
with different N opcodes.

Step 1: The address portion of IR is loaded into the MAR.

Step 2: The address field of the IR is updated from the MBR, so the reference memory
location is read.
 The Indirect Cycles
Once an instruction is fetched, the next step is to fetch source operands. Source Operand is
being fetched by indirect addressing( it can be fetched by any addressing mode, here its done
by indirect addressing). Register-based operands need not be fetched. Once the opcode is
executed, a similar process may be needed to store the result in main memory.
Following micro-operations takes place:-

Step 1: The address field of the instruction is transferred to the MAR. This is used to fetch the

address of the operand.

Step 2: The address field of the IR is updated from the MBR.(So that it now contains a direct

addressing rather than indirect addressing)

Step 3: The IR is now in the state, as if indirect addressing has not been occurred. Note: Now
 Advantages of instruction cycle
• Standardization: The instruction cycle provides a standard way for CPUs to execute

instructions, which allows software developers to write programs that can run on

multiple CPU architectures. This standardization also makes it easier for hardware

designers to build CPUs that can execute a wide range of instructions.

• Efficiency: By breaking down the instruction execution into multiple steps, the CPU

can execute instructions more efficiently. For example, while the CPU is performing

the execute cycle for one instruction, it can simultaneously fetch the next instruction.

• Pipelining: The instruction cycle can be pipelined, which means that multiple

instructions can be in different stages of execution at the same time. This improves

the overall performance of the CPU, as it can process multiple instructions

simultaneously.
 Disadvantages of instruction cycle
• Overhead: The instruction cycle adds overhead to the execution of instructions, as

each instruction must go through multiple stages before it can be executed. This

overhead can reduce the overall performance of the CPU.

• Complexity: The instruction cycle can be complex to implement, especially if the CPU

architecture and instruction set are complex. This complexity can make it difficult to

design, implement, and debug the CPU.

• Limited parallelism: While pipelining can improve the performance of the CPU, it

also has limitations. For example, some instructions may depend on the results of

previous instructions, which limits the amount of parallelism that can be achieved. This

can reduce the effectiveness of pipelining and limit the overall performance of the

CPU.
 Pipelining
• Pipelining is the process of accumulating instruction from
the processor through a pipeline.
• It allows storing and executing instructions in an orderly
process.
• It is also known as pipeline processing.
• Pipelining is a technique where multiple instructions are
overlapped during execution.
• Pipeline is divided into stages and these stages are
connected with one another to form a pipe like structure.
• Instructions enter from one end and exit from another
end.
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 Pipelining
• Pipeline is divided into stages and these stages
are connected with one another to form a
pipe like structure.
• In a pipeline system, each stage/segment
consists of an input register followed by a
combinational circuit.
• The register is used to hold data and
combinational circuit perform operation on it.

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 Pipelining

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 Pipelining :Types
• It is divided into 2 categories:
1. Arithmetic Pipeline
2. Instruction Pipeline
• Arithmetic pipelines are usually found in most of
the computers. They are used for floating point
operations, multiplication of fixed point numbers
etc
• In Instruction Pipeline a stream of instructions
can be executed by overlapping fetch, decode and
execute phases of an instruction cycle
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 Instruction Pipeline
• In this a stream of instructions can be executed by overlapping fetch,

decode and execute phases of an instruction cycle.

• This type of technique is used to increase the throughput of the

computer system.

• An instruction pipeline reads instruction from the memory while

previous instructions are being executed in other segments of the

pipeline.

• Thus we can execute multiple instructions simultaneously.

• The pipeline will be more efficient if the instruction cycle is divided into
 Instruction Pipeline

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 Instruction Pipelining : Decomposition

In the most general case computer needs to process each

instruction in following sequence of steps:

• Fetch the instruction from memory (FI)

• Decode the instruction (DA)

• Calculate the effective address(CO)

• Fetch the operands from memory (FO)

• Execute the instruction (EX)

• Store the result in the proper place(WO)

 Instruction Pipelining

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 Instruction Pipelining : Branch Instruction

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 Instruction Pipelining : Branch Instruction

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 Instruction Pipelining

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Example:
 Cont..
• Here the instruction is fetched on first clock cycle in segment 1.

Now it is decoded in next clock cycle, then operands are fetched and finally the

instruction is executed. We can see that here the fetch and decode phase overlap

due to pipelining. By the time the first instruction is being decoded, next

instruction is fetched by the pipeline.

• In case of third instruction we see that it is a branched instruction. Here when it is

being decoded 4th instruction is fetched simultaneously. But as it is a branched

instruction it may point to some other instruction when it is decoded. Thus fourth

instruction is kept on hold until the branched instruction is executed. When it gets

executed then the fourth instruction is copied back and the other phases continue as
 Performance evolution factor for pipelined
computer
• clock period
• Speedup
• Efficiency
• Throughput

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 Performance of Pipelined Execution
The following parameters serve as criterion to
estimate the performance of pipelined execution.
1. Speed Up-
It gives an idea of “how much faster” the
pipelined execution is as compared to non-
pipelined execution.
It is calculated as:
 2. Efficiency
The efficiency of pipelined execution is calculated as-
 3. Throughput-

Throughput is defined as number of instructions executed

per unit time.
 What are Pipeline Hazards?
• A pipeline hazard occurs when the pipeline, or some portion of the pipeline,

must stall because conditions do not permit continued execution.

• Such a pipeline stall is also referred to as a pipeline bubble

• Some instructions will become dependent on one another, reducing the

pipeline’s pace. The dependencies in the pipeline are referred to as hazards

since they put the execution at risk.

• We can swap the terms, dependencies and hazards since they are used

interchangeably in computer architecture.

• A hazard, in essence, prevents an instruction present in the pipe from being

performed during the specified clock cycle.

 Types of Pipeline Hazards

The three different types of hazards in computer

architecture are:

1. Structural (Resource)

2. Data

3. Control
 Structural Hazard
• Hardware resource conflicts among the instructions in the pipeline cause

structural hazards.

• A resource hazard occurs when two (or more) instructions that are

already in the pipeline need the same resource.

• A resource here could be the Memory, a Register in GPR or ALU

• This resource conflict is said to occur when more than one instruction in

the pipe is requiring access to the same resource in the same clock cycle

• The result is that the instructions must be executed in serial rather than

parallel for a portion of the pipeline.

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 Structural Hazard : Solution

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 Structural Hazard : Solution
• The pipeline may be increased to 5 or more stages and
suitably redefine the functionality of the stages and adjust the
clock frequency.
• This eliminates the issue of the hazard at every 4th instruction
in the 4-stage pipeline
• The memory may physically be separated as Instruction
memory and Data Memory.
• A Better choice would be to design as Cache memory in CPU,
rather than dealing with Main memory.
• IF uses Instruction memory and Result writing uses Data
Memory.
• These become two separate resources avoiding dependency.
• It is possible to have Multiple levels of Cache in CPU too.
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 Structural Hazard : Solution
• There is a possibility of ALU in resource
dependency. ALU may be required in IE machine
cycle by an instruction while another instruction
may require ALU in IF stage to calculate Effective
Address based on addressing mode. The solution
would be either stalling or have an exclusive ALU
for address calculation.
• Register files are used in place of GPRs. Register
files have multiport access with exclusive read and
write ports. This enables simultaneous access on
one write register and read register.
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 Data Hazards
• Data hazards in pipelining emerge when the execution of
one instruction is dependent on the results of another
instruction that is still being processed in the pipeline.
ADD AX,BX
SUB CX,AX
• The order of the READ or WRITE operations on the
register is used to classify data threats into three groups.
 Data Hazards : Types
• Read after write (RAW), or true dependency: A hazard occurs if
the read takes place before the write operation is complete.
• Write after read (RAW), or antidependency: A hazard occurs if
the write operation completes before the read operation takes
place.
• Write after write (RAW), or output dependency: Two
instructions both write to the same location. A hazard occurs if
the write operations take place in the reverse order of the
intended sequence.
 Control Hazards
• Branch hazards are caused by branch instructions and are known as control

hazards in computer architecture.

• The flow of program/instruction execution is controlled by branch

instructions. Remember that conditional statements are used in higher-level

languages for iterative loops and condition testing (correlate with while,

for, and if case statements).

• These are converted into one of the BRANCH instruction variations. As a

result, when the decision to execute one instruction is reliant on the result

of another instruction, such as a conditional branch, which examines the

condition’s consequent value, a conditional hazard develops.