REGISTERS AND
COUNTERS
Module 5
Registers and Counters: Registers: Types of registers, Application of shift
registers HDL implementation: HDL implementation of registers,Asynchronous
counters, Decoding gates, Synchronous counters, changing the counter modulus,
decade counters, presettable counters , counter design as a synthesis problem,
Design of sequential circuits: Design of synchronous sequential circuits ,
Sequential Parity checker
● A register is a very important digital building block.
● A data register is often used to momentarily store binary information
appearing at the output of an encoding matrix.
● A register might be used to accept input data from an alphanumeric
keyboard and then present this data at the input of a microprocessor chip.
● Similarly, registers are often used to momentarily store binary data at the
output of a decoder.
● Thus registers form a very important link between the main digital system
and the input-output channels.
TYPES OF REGISTERS
● A binary register also forms the basis for some very important arithmetic
operations.
● For example, the operations of complementation, multiplication, and
division are frequently implemented by means of a as sequence generator
and sequence detector and also as parallel to serial converters offers very
distinct advantages register.
● A shift register can also be connected to form a number of different types
of counters.
● Shift registers as sequence generator and sequence detector and also as
parallel to serial converters offers very distinct advantages
TYPES OF REGISTERS
• A register is simply a group of flip-flops that can be used to store a binary number.
"There must be one flipflop for each bit in the binary number.
• For instance, a register used to store an 8-bit binary number must have eight flip-
flops.
• Naturally the flip-flops must be connected such that the binary number can be
entered ( shifted) into the register and possibly shifted out.
• A group of flip-flops connected to provide either or both of these functions is called a
shift register.
TYPES OF REGISTERS
• The bits in a binary number (let's call them the data) can be moved from one
place to another in either of two ways.
• The first method involves shifting the data 1 bit at a time in a serial fashion,
beginning with either the most significant bit (MSB) or the least significant bit
(LSB).
• This technique is referred to as serial shifting. The second method involves
shifting all the data bits simultaneously and is referred to as parallel shifting
TYPES OF REGISTERS
• There are two ways to shift data into a register (serial or parallel) and similarly
two ways to shift the data out of the register.
• This leads to the construction of four basic register types as shown in Fig. 9.l-
serial in serial out, serial in-parallel out, parallel in-serial out, and parallel in-
parallel out.
• All of these configurations are commercially available as TTL MSI/LSI
circuits. For instance:
TYPES OF REGISTERS
Serial in-serial out-54/74LS91, 8 bits
Serial in-parallel out-54/74164, 8 bits
Parallel in-serial out-54/74165, 8 bits
Parallel in-parallel out-54/74198, 8 bits
APPLICATIONS Of SHIFT REGISTERS
● Shift registers are used in almost every sphere of a digital logic system. In this section
we discuss few such applications.
● Shift register can be used to count number of pulses entering into a system as ring
counter or switched-tail counter.
● As ring counter it can generate various control signals in a sequential manner.
● Shift register can also generate a prescribed sequence repetitively or detect a particular
sequence from data input.
● It can also help in reduction of hardware by converting parallel data feed to serial one.
Ring Counter
● Let's begin with a simple serial shift register such as the
54/74164. One of the most logical applications of feedback
might be to connect the output of the last flip-flop QH back to
the D input of the first flip-flop A
Ring Counter
• Notice that the A and B data inputs are connected together.
Now, suppose that all flip-flops are reset and the clock is
allowed to run. What will happen?
• The answer is, nothing will happen since the D input to the
first flip-flop is low (the input at A and B).
• Therefore, every time the clock goes high, the zero in each
flip-flop will be shifted into the next flip-flop, while the
zero in the last flip-flop H will travel around the feedback
loop and shift into the first flip-flop A.
Ring Counter
• Consider the register as a tube full of zeros (ping-pong balls) that shift round
and round the register, moving ahead one flip-flop with each clock PT.
• Suppose that QA is high and all other flip-flops are low, and then allow the
clock to run. On the very first clock PT, the 1 in A will shift into B and A will
be reset, since the 0 in H will shift into A.
• All other flip-flops will still contain 0s. The second clock pulse will shift the
1 from B to C, while B resets. The third clock PT will shift the 1 from C to
D, and so on.
• Thus this single 1 will shift down the register, traveling from one flip-flop to
• When it reaches flipflop H, the next clock PT will shift it into flip-flop
A by means of the feedback connection.
• Again, consider the register as a tube full of ping-pong balls, seven
"white" ones (Os) and one "black" one (a 1).
• The ping-pong balls simply circulate around the register in a clockwise
direction, moving ahead one flip-flop with each clock PT.
• This configuration is frequently referred to as a circulating register or
a ring counter.
Ring Counter
• The waveforms present in this ring counter are given in Fig.
9.20b.
Ring Counter
• In order to produce the waveforms shown in Fig.9 .20, the counter should have one,
and only one, 1 in it.
• The chances of this occurring naturally when power is first applied are very remote
indeed.
• If the flip-flops should all happen to be in the reset state when power is first applied, it
will not work at all, as we saw previously.
• On the other hand, if some of the flip-flops come up in the set state while the remainder
come up in the reset state, a series of complex waveforms of some kind will be the
result.
• Therefore, it is necessary to preset the counter to the desired state before it can be used.
Switched-Tail Counter or Johnson Counter
If we feed inverting output back (or switch the tail) as shown
in Fig. 9.22a for a 4-bit shift register we get switched tail
counter, also known as twisted tail counter or Johnson
counter
Switched-Tail Counter or Johnson Counter
• Assume all the flip-flops are cleared in the beginning.
• Then all the flip-flop inputs have 0 except the first one, serial
data in which is complement of the last flip-flop, i.e. 1.
• When clock trigger occurs flip-flop stores QRST as I 000. This
makes 1100 at the input of QRST when the next clock trigger
comes and that gets transferred to output at NT.
• Proceeding this we complete state table of Fig. 9.22b. Note
that output Y = Q'T' and state of the circuit repeats every
eighth clock cycle.
• Thus this 4-bit shift register circuit can count 8 clock pulses
or called modulo-8 counter.
Switched-Tail Counter or Johnson Counter
• Following above logic and preparing state table for any N-bit
shift register we see switched-tail configuration can count up to
2N number of clock pulse and gives modulo-2N counter.
• The output Y, derived similarly by AND operation of first and
last flip-flop inverting outputs gives a logic high at every 2N-th
clock cycle.
• There is another important issue related with ring counter
and switched tail counter.
• An n-bit register has 2n different combination of states.
But, the counter is to be initialized with one of the valid
state of the counting sequence on which the design is based.
Linear Feedback Shift Register
LFSR
● Linear feedback Shift Register uses only Ex-Or
functions which gives sum logic.
● It can give maximum 2n -1 different states which
excludes all zero values.
● We redraw 4-bit shift register with D flip-flops of
fig-9.22a little differently and designate the
output Q,R,S,T as x1,x2,x3,x4 respectively.
● The serial input is designed as x0.
Linear Feedback Shift Register
● This form is represented with delay operator
applied to an input data.
● When input reaches the output of the first flip flop
then one delay operation has taken place.
● At the second flip flop output we have delay of
delay.
● This gives a simple polynomial form of
representation of LFSR.
● Representation of polynomial x4+x3+1.
LSFR
● It can be initialized with any value but 0000..
● Then we get the maximal length sequence
which is 15 cycle long.
● LSFR can be maximal-length if number of
taps are even or the tap numbers should be
relatively prime in a set.
For the polynomial x3+x2+1 , the table shows
that the maximum sequence is not generated.
Sequence Generator and Sequence Detector
Sequence generator is useful in generating a sequence
pattern repetitively.
It may be the synchronizing hit pattern sent by a digital
data transmitter or it may be a control word directing
repetitive control task.
Sequence detector checks binary data stream and
generates a signal when a particular sequence is
detected.
Figure 9.23a gives the basic block diagram of a
sequence generator where shift register is presented
as pipe full of data and each flip-flop represents one
compartment of it.
The leftmost flip-flop is connected to serial data in
and rightmost provides serial data out.
The clock is implied and data transfer takes place
Note that the shift register is connected like a ring
counter and with triggering of clock the binary
word stored in the clock comes out sequentially
from serial out but does not get lost as it is fed
back as serial in to fill the register all over again.
The circuit that can detect a 4-bit binary
sequence is shown in Fig. 9.23b.
It has one register to store the binary word we
want to detect from the data stream.
Input data stream enters a shift register as serial
data in and leaves as serial out.
At every clocking instant, bit-wise comparisons of these two
registers are done through Ex-NOR gate as shown in the
figure.
Two input Ex-NOR gives logic high when both inputs are low
or both of them are high, i.e. when both are equal.
The final output is taken from a four input AND gate, which
becomes 1 only when all its inputs are 1, i.e. all the bits are
matched.
Figure 9.23b shows a situation when data received
so far is O 111 and word to be matched is 1011.
The first two bits are mismatched and
corresponding Ex-NOR outputs are low, so also
final output Y.
Now, as the next bit in the serial data stream is 1 when a
clock trigger comes the first flip-flop of the shift-register
stores 1 and O 11 gets shifted to 2nd to 3rd flip-flops.
With this both registers store 1011 and the first flip-flop of
the shift-register stores 1 and 011 gets shifted to 2nd to
3rd flip-flops and Y = l completing sequence detection.
Note that Fig. 9.23b can be used as a programmable
sequence detector, i.e. if we want to change the binary word
to be detected we simply load that in the bottom register.
For a fixed sequence detector, we can reduce hardware cost by
removing bottom register and directly connect Ex-NOR input to
+Vcc or GND depending on whether we need a 1 or a O to be
detected in a particular position.
Serial Adder
Using shift register to implement Full adder
circuit that adds Two 8-bit numbers
Figure 9.24 shows how serial addition takes
place in a time-multiplexed manner and also
provides a snapshot of the register values at 3rd
clock cycle:
Two 8-bit numbers, to be added (A7A6 ... A1A0 and B7B6···B1Bo) are
loaded in two 8-bit shift registers A and B.
The LSB of each number appears in the rightmost position in two
registers.
Serial data out of A and B are fed to data inputs of full adder.
The carry-in is fed from its own carry output delayed by one clock
period by a D flip-flop, which is initially cleared.
Both registers and D flip-flop are triggered by same clock. The sum
(S) output of FA is fed to serial data in of Shift Register A.
The serial addition takes place like this.
The LSBs of two numbers (Ao and Bo) appearing at serial out
of respective registers are added by FA during 1st clock cycle
and generate sum (S0) and carry (C0).
S0 is available at serial data input of register A and C0 at
input of D flip-flop.
At NT of clock shift registers shift its content to right by one
unit. S0 becomes MSB of A and C0 appears at D flip-flop
output.
Therefore in the second clock cycle FA is fed by
second bit (A I and B 1) of two numbers and
previous carry ( C0).
In second clock cycle, S1 and C1 are generated
and made available at serial data in of A register
and input of D flip-flop respectively.
At NT of clock S1 becomes MSB of A and So
occupies next position. A2 and B2 now appear at
In 3rd clock cycle, S2 and C2 are generated and they
get transferred similarly to register and flip-flop.
This process goes on and is stopped by inhibiting the
clock after 8 clock cycles.
At that time shift register A stores the sum bits, S7
in leftmost (MSB) position and So in rightmost (LSB)
position.
The final carry is available at D flip-flop output.
The limitation of this scheme is that the final
addition result is delayed by eight clock cycles.
In parallel adder the result is obtained almost
instantaneously, after nanosecond order
propagation delay of combinatorial circuit.
However, using a high frequency clock the delay
factor can be reduced considerably.
REGISTER IMPLEMENTATION IN HDl
Consider the parallel in parallel out register,
primarily used for storage purpose
Tis the final output and Q,R, S are internal outputs.
Since they are outputs of always block they have
to be defined as reg and not wire.
Note that, we use a new assignment operator<=
within always block which unlike = operator
executes all associated statements concurrently.
If we had used= instead of<=, the D input
through sequential execution would have
reached final output in one clock cycle (unlike 4
clock cycles required in 4-bit shift register), also
all the flip-flops within the register will have
same value that of serial data input.
Often, use of = operator is called blocking mode
operation and use of<= is called non blocking
A 4-bit serial in parallel out right shift register where
all the flip-flop outputs are available externally. We
use vector notation for convenience wherever
possible.
Verilog code for switched tail counter
Design an 8-bit sequence generator that
generates the sequence 11000 l 00 repetitively
using shift register.
Counters
● A counter is probably one of the most useful
and versatile subsystems in a digital system.
● A counter driven by a clock can be used to
count the number of clock cycles.
● There are basically two different types of
counters-synchronous and asynchronous.
Counters
● The ripple counter is simple and straightforward
in operation and its construction usually
requires a minimum of hardware.
● It does, however, have a speed limitation.
● Each flip-flop is triggered by the previous flip-
flop, and thus the counter has a cumulative
settling time. Counters such as these are called
serial, or asynchronous.
Counters
● An increase in speed of operation can be
achieved by use of a parallel or
synchronous counter.
● Here, every flip-flop is triggered by the clock
(in synchronism), and thus settling time is
simply equal to the delay time of a single flip-
flop. The increase in speed is usually
obtained at the price of increased hardware
Counters
● Serial and parallel counters are used in
combination to compromise between speed
of operation and hardware count.
ASYNCHRONOUS COUNTERS
Ripple Counters
● A binary ripple counter can be constructed using clocked JK flip-
flops. Figure 10.1 shows three negative edge- triggered, JK flip-
flops connected in cascade.
● The system clock, a square wave, drives flip-flop A.
● The output of A drives B, and the output of B drives flip-flop C. All
the and K inputs are tied to +Vcc·
● This means that each flip-flop will change state (toggle) with a
negative transition at its clock input.
Ripple Counters
● When the output of a flip-flop is used as the clock
input for the next flip-flop, we call the counter a
ripple counter, or asynchronous counter.
● The A flip-flop must change state before it can
trigger the B flip-flop, and the B flip-flop has to
change state before it can trigger the C flip-flop.
Ripple Counters
● The triggers move through the flip-flops like a
ripple in water. Because of this, the overall
propagation delay time is the sum of the
individual delays.
● For instance, if each flip-flop in this three-flip-
flop counter has a propagation delay time of 10
ns, the overall propagation delay time for the
counter is 30 ns.
Ripple Counters
● The waveforms given in Fig. 10.l b show the
action of the counter as the clock runs.
● Let's assume that the flip-flops are all initially
reset to produce O outputs.
● If we consider A to be the least-significant
bit(LSB) and C the most-significant bit (MSB),
we can say the contents of the counter is
CBA = 000.
● Every time there is a clock NT, flip-flop A will
change state. This is indicated by the small
arrows downwards on the timeline.
● Notice that the waveform at the output of
flip-flop A is one-half the clock frequency.
Ripple Counters
● Since A acts as the clock for B, each time the
waveform at A goes low, flip-flop B will toggle.
● Thus at point b on the time line, B goes high; it
then goes low at point d and toggles back high
again at point f.
● Notice that the waveform at the output of flip-
flop Bis one-half the frequency of A and one-
fourth the clock frequency.
●
● Since B acts as the clock for C, each time the
waveform at B goes low, flip-flop C will
toggle. Thus C goes high at point d on the
time line and goes back low again at point h.
● The frequency of the waveform at C is one-
half that at B, but it is only one-eighth the
clock frequency.
Ripple Counters
● Since a binary ripple counter counts in a straight
binary sequence, it is easy to see that a counter
having n flip-flops will have 2n output conditions.
● For instance, the three-flip-flop counter just
discussed has 23 = 8 output conditions (000 through
111).
● Five flip-flops would have 25 = 32 output conditions
(00000 through 11111 ), and so on.
● The largest binary number that can be
represented by n cascaded flip-flops has a
decimal equivalent of 2n - 1.
● For example, the three-flip-flop counter reaches
a maximum decimal number of 23 - 1. The
maximum decimal number for five flip-flops is 25
- l = 31, while six flip-flops have a maximum
count of 63.
Ripple Counters
The 54/7 493A
The logic diagram, DIP
pinout, and truth table
for a 5417493A are
given in Fig. on the
right.
This TTL MSI circuit is
a 4-bit binary counter
that can be used in
either a mod-8 or a
mod-16 configuration.
Ripple Counter
● If the clock is applied at input CKB, the outputs
will appear at QB, Qc, and QA, and this is a mod-8
binary ripple counter exactly like that in Fig. 10.L
● In this case, flip-flop QA is simply unused.
● If the clock is applied at input CKA and flip-flop
QA is connected to input CKB, we have a mod-16,
4-bit binary ripple counter. The outputs are QA,
QB, Qc, and QD.
● All the flip-flops in the 7493A have direct reset
Draw the correct output waveforms for a 7493A connected as a
mod-16 counter.
Ripple Counter
● An interesting and useful variation of the 3-bit ripple counter in
Fig. 10.1 is shown in Fig. 10.4.
● The system clock is still used at the clock input to flip-flop A, but
the complement of A, A, is used to drive flipflop B, likewise; B is
used to drive flip-flop C. Flip-flop A simply toggles with each
negative clock transition as before. But flip-flop B will toggle each
time A goes high! Notice that each time A goes high, A goes low,
and it is this negative transition on A that triggers B. On the time
line, B toggles at points a, c, e, g and i.
Ripple Counter
● Similarly, flip-flop C is triggered by B and so C will toggle each time B goes
high.
● Thus C toggles high at point a on the time line, toggles back low at point e
and goes back high again at point i.
● The counter contents become ABC= 111 at point a on the time line,
change to 110 at point b, and change to 101 at point c.
● Notice that the counter contents are reduced by one count with each clock
transition! In other words, the counter is operating in a count-down mode.
● The results are summarized in the truth table in Fig. 10.4c. This is still a
mod-8 counter, since it has eight discrete states, but it is connected as a
down counter.
Decoding Gates
● A decoding gate can be connected to the
outputs of a counter in such a way that the
output of the gate will be high (or low) only
when the counter contents are equal to a given
state.
● For instance, the decoding gate connected to the 3-bit
ripple counter in Fig. 10.6a will decode state 7 ( CBA =
111 ).
● Thus the gate output will be high only when A = 1, B =
I, and C = 1 and the waveform appearing at the output
of the gate is labeled 7.
● The Boolean expression for this gate can be written 7 =
CBA. A comparison with the truth table for this counter
(in Fig. 10.1) will reveal that the condition CBA = 111 is
true only for state 7.
Decoding Gates
Decoding Gates
● The other seven states of the counter can be decoded in a similar
fashion.
● It is only necessary to examine the truth table for the counter and then
the proper Boolean expression for each gate can be written.
● For instance, to decode state 5, the truth table reveals that CBA = 101 is
the unique state.
● For the gate output to be high during this time, we must use C, B, and A
at the gate inputs.
● Notice carefully that if B = 0, then B’=1!
● The correct Boolean expression is then 5 = CB’A, and the desired gate is
that given in Fig. 10.6c.
● The is again that given in Fig. 10.6b and is labeled 5.
Decoding Gates
Decoding Gates
● All eight gates necessary to decode the eight states of the 3-bit
counter in Fig. 10.1 are shown in Fig. 10. 7a.
● The gate outputs are shown in Fig. 10. 7b. These decoded
waveforms are a series of positive pulses that occur in a strict time
sequence and are very useful as control signals throughout a
digital system.
● If we consider state O as the first event, then state 1 will be the
second, state 2 the third, and so on, up to state 7.
● Clearly the counter is counting upward in decimal notation from O
to 7 and then beginning over again at 0.
Synchronous Counter
● The ripple counter is the simplest to build, but there is a
limit to its highest operating frequency.
● As previously discussed, each flip-flop has a delay time.
● In a ripple counter these delay times are additive, and
the total "settling" time for the counter is approximately
the delay time times the total number of flip-flops.
● Furthermore, there is the possibility of glitches
occurring at the output of decoding gates used with
a ripple counter.
Synchronous Counter
The first problem fully and the second problem, to some
extent can be overcome by the use of a synchronous
parallel counter.
The main difference here is that every flip-flop is
triggered in synchronism with the clock.
Synchronous Counter
The clock is applied directly to flip-flop A.
Since the JK flip-flop used responds to a negative
transition
at the clock input and toggles when both the J and
K inputs are high, flip-flop A will change state with
each clock NT.
Whenever A is high, AND gate X is enabled and a
clock pulse is passed through the gate to the clock
input of flip-flop B.
Thus B changes state with every other clock NT at
points b, d,f, and h on the time line.
Since, there is an additional AND gate delay for the
clock at B flip-flop in comparison to A flip-flop, it is not
a parallel counter in a strict sense of the term.
An irregular counter is the one which does not
follow any regular binary sequence but has N
number of distinct states and thus qualifies as a
modulo-N counter.
A condition may exist in a counter taking the
counter from one unused state to another unused
state and not allowing to come back to any used
states. Such condition is called as Lock out
condition,.
A self correcting counter is a counter which has
all the abnormal/ unused states having
transitions leading them to used / normal states.
Design a self-correcting modulo-6 counter as
described in which all the unused state leads to
state CBA = 000.
Design problem normally starts with a word
description of input output relation and ends with
a circuit diagram having sequential and
combinatorial logic elements.
The word description is first converted to a state
transition diagram or Algorithmic State Machine
(ASM) chart followed by preparation of state
synthesis table.
For flip-flop based implementation, excitation
tables are used to generate design equations
through Karnaugh Map.
The final circuit diagram is developed from
these design equations.
There are two different approaches of state
machine design called Moore model and Mealy
model.
In Moore model circuit outputs, also called
primary outputs are generated solely from
secondary outputs or
memory values.
In Mealy model circuit inputs, also known as
primary inputs combine with memory elements
In Moore model (Fig. [Link]) the output depends
only on present state and not on input.
In Mealy model (Fig. [Link]), the output is derived
from present state as well as input.