CMOS PROCESS
TECHNOLOGY
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CMOS Fabrication:
When we need to fabricate nMOS and pMOS transistors on the
same substrate, we need to follow different processes.
The three different processes are
1. P-well,
2. N-well, and
3. Twin tub processes.
N-well
Fabrication
Process
TYPES OF FABRICATION
PROCESS
STEP 1: SUBSTRATE
First we choose a substrate as a base for fabrication.
For N-well, a P-type silicon substrate is selected.
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STEP 2: OXIDATION
The selective diffusion of n-type impurities is accomplished
using SiO2 as a barrier which protects portions of the wafer
against contamination of the substrate.
SiO2 is laid out by an oxidation process done by exposing the
substrate to high-quality oxygen and hydrogen in an oxidation
chamber at approximately 1000’c
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STEP 3: PHOTORESIST
At this stage to permit the selective etching, the SiO2
layer is subjected to the photolithography process.
In this process, the wafer is coated with a uniform film of
a photosensitive emulsion.
A light-sensitive polymer that softens whenever exposed
to light is called a Photoresist layer. It is formed.
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STEP 4: MASKING
This step is the continuation of the photolithography process.
In this step, a desired pattern of openness is made using a
stencil. This stencil is used as a mask over the photoresist.
The substrate is now exposed to UV rays the photoresist
present under the exposed regions of the mask gets
polymerized.
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STEP 5: PHOTORESIST
REMOVAL
The mask is removed and the unexposed region of
photoresist is dissolved by developing wafer using a
chemical solution such as Trichloroethylene.
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STEP 6: REMOVAL OF SIO2
USING ACID ETCHING
The SiO2 oxidation layer is removed through the open area
made by the removal of photoresist using hydrofluoric acid.
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STEP 7: REMOVAL OF
PHOTORESIST
During the etching process, those portions of SiO2
which are protected by the photoresist layer are not
affected.
The photoresist mask is now stripped off with a chemical
solvent (hot H2SO4).
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STEP 8: FORMATION OF THE
N-WELL
The n-type impurities are diffused into the p-type
substrate through the exposed region thus forming an
N- well.
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STEP 9: REMOVAL OF SIO2
Using the hydrofluoric acid, the remaining SiO2 is
removed.
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STEP10: DEPOSITION OF
POLYSILICON
The misalignment of the gate of a CMOS transistor would lead to unwanted
capacitance which could harm the circuit.
So to prevent this “Self-aligned gate process” is preferred where gate regions
are formed before the formation of source and drain using ion implantation.
Polysilicon is used to form the gate because it can withstand a high
temperature greater than 8000’c when a wafer is subjected to annealing
methods for the formation of source and drain. Polysilicon is deposited by
using the Chemical Deposition Process over a thin layer of gate oxide.
This thin gate oxide under the Polysilicon layer prevents further doping under
the gate region.
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STEP 11: REMOVING THE LAYER
BARRING A SMALL AREA FOR THE
GATES
Except the two regions required for the formation of
the gate for NMOS and PMOS transistors the
remaining portion of Polysilicon is stripped off.
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STEP12: OXIDATION PROCESS
An oxidation layer is deposited over the wafer which
acts as a shield for further diffusion and metallization
processes.
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STEP 13: MASKING AND N-
DIFFUSION
By using the masking process small gaps are made for
the purpose of N-diffusion.
The n-type (n+) dopants are diffused or ion-implanted,
and the three n+ are formed for the formation of the
terminals of NMOS.
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STEP14: OXIDE STRIPPING
The remaining oxidation layer is stripped off.
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STEP15: P-DIFFUSION
Similar to the n-type diffusion for forming the terminals of
PMOS p-type diffusion are carried out.
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STEP16: THICK FIELD
OXIDE
Before forming the metal terminals a thick field oxide is
laid out to form a protective layer for the regions of the
wafer where no terminals are required.
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STEP17: METALLIZATION
This step is used for the formation of metal terminals
which can provide interconnections.
Aluminum is spread on the whole wafer.
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STEP18: REMOVAL OF EXCESS
METAL
The excess metal is removed from the wafer
layer.
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STEP 19: TERMINALS
The terminals of the PMOS and NMOS are made from
respective gaps.
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STEP20: ASSIGNING THE NAMES
OF THE TERMINALS OF THE
NMOS AND PMOS
FINAL IC
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P-WELL PROCESS :
The fabrication steps of p well process are same as that of an n-well process except
that instead of n-well a p-well is implanted .
The process steps involved in p-well process are shown in Figure below.
The process starts with the n type substrate.
Step 1: A thin layer of SiO2 is deposited which will serve as the pad oxide.
Step 2: A thicker sacrificial silicon nitride layer is deposited by chemical vapor
deposition (CVD).
Step 3: A plasma etching process is used to create trenches used for insulating the
devices.
Step 4: The trenches are filled with SiO2 which is called the field oxide.
Step 5: To provide a flat surface chemical mechanical planerization is performed and
also sacrificial nitride and pad oxide are removed.
Step 6: The p-well mask is used to expose only the p-well areas, after this implant an
annealing sequence is applied to adjust the well doping. This is followed by a second
implant step to adjust the threshold voltage of the NMOS transistor.
Step 7: The implant step is performed to adjust the threshold voltage of the PMOS
transistor.
Step 8: A thin layer of gate oxide and polysilicon is chemically deposited and patterned
with the help of a polysilicon mask.
Step 9: Ion implantation to dope the source and drain regions of the PMOS (p+) and NMOS
(n+) transistors, this will also form n + polysilicon gate and p+ polysilicon gate for NMOS
and PMOS transistors respectively. Hence this process is called a self-aligned process.
Step 10: Then the oxide and nitride spacers are formed by chemical vapor deposition.
Step 11: In this step contact or via holes are etched, and metal is deposited and patterned.
After the deposition of the last metal layer final passivation or overglass is deposited for
protection.
TWIN WELL PROCESS
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DUAL-WELL PROCESS OR TWIN-TUB
PROCESS :
In the Dual-well process, both p-well and n-well for NMOS
and PMOS transistors respectively are formed on the same
substrate.
The main advantage of this process is that the threshold
voltage, body effect parameter, and transconductance can
be optimized separately.
The starting material for this process is a p+ substrate with
an epitaxially grown p-layer which is also called an
epilayer.
The process starts with a p-substrate surfaced with a lightly
doped p-epitaxial layer.
Step 1: A thin layer of SiO2 is deposited which will serve as the
pad oxide.
Step 2: A thicker sacrificial silicon nitride layer is deposited by
chemical vapor deposition.
Step 3: A plasma etching process is used to create trenches used
for insulating the devices.
Step 4: The trenches are filled with SiO2 which is called the
field oxide.
Step 5: To provide a flat surface chemical mechanical planarization is performed and also
sacrificial nitride and pad oxide are removed.
Step 6: The p-well mask is used to expose only the p-well areas, after this implant and annealing
sequence is applied to adjust the well doping. This is followed by the second implant step to
adjust the threshold NMOS transistor.
Step 7: The n-well mask is used to expose only the n-well areas, after this implant and annealing
sequence is applied to adjust the well doping. This is followed by a second implant step to adjust
the threshold voltage of the PMOS transistor.
Step 8: A thin layer of gate oxide and polysilicon is chemically deposited and patterned
with the help of a polysilicon mask.
Step 9: Ion implantation to dope the source and drain regions of the PMOS (p +) and
NMOS (n+) transistors is used this will also form an n+ polysilicon gate and p+ polysilicon
gate for NMOS and PMOS transistors respectively.
Step 10: Then the oxide or nitride spacers are formed by chemical vapor deposition (CVD).
Step 11: In this step contact or holes are etched, metal is deposited and patterned. After the
deposition of the last metal layer final passivation or overglass is deposited for protection.
SOI
TECHNOLOGY
Silicon on Insulator (SOI)
Silicon on Insulator (SOI) is a semiconductor wafer technology that
produces higher performing, lower power (dynamic) devices than
traditional bulk silicon techniques.
SOI works by placing a thin insulating layer, such as silicon oxide or
glass, between a thin layer of silicon and the silicon substrate.
This process helps reduce the amount of electrical charge that the
transistor has to move during a switching operation, thus making it faster
and allowing it to switch using less energy.
SOI chips can be as much as 15 percent faster and use 20 percent less
power than today's bulk complementary metal-oxide semiconductor
(CMOS)-based chips.
Introduced as an alternative CMOS technology in 1978, silicon-on-
insulator(SOI) technology offers:
Potential For High Speed
Low Power Consumption
Soft-error Reduction
Latch-up Immunity
Manufacturing Process Simplification
Improved Scaling
The steps used in typical SOI CMOS processes are as
follows:
Step 1: A silicon-on-insulator semiconductor substrate, comprising:
1. a silicon wafer:
2. a first oxide layer formed on the upper surface of the first silicon
layer usually sapphire or SiO2 is used as an insulator.
3. an undoped poly-silicon layer (ie) A thin film (.5 to 4 µm) of very
lightly doped N-type Si is grown over the upper surface of the
polysilicon layer.
Step 2:
1. using an anisotropic etching the n and p areas are formed using
diffusion.
2. The p-islands are formed next by masking the n-wells with a
photoresist. A p-type dopant, boron for example is then implanted
3. The p-island formed by the photoresist become an n-channel
device. See (b & c)
Step 3:
1. The p-islands are then covered with a photoresist and an n-type
dopant. For example, phosphorus is implanted to form the n-
islands.
2. The n-islands will become the p-channel devices. See Figure
1.22 (d & e)
Step 4
1. The first formation of p-island and n-island is covered with thin
gate oxide around 100 - 250 A’is grown over all of the Si
structures to have isolation between different layers.
2. This process is accomplished by thermal oxidation. Generally,
when forming an oxide layer on a silicon layer under a high-
temperature environment, various electric charges are formed
on the surface of the silicon layer.
Step 5
To reduce the resistivity of different layers, a polysilicon usually
phosphorus is deposited over the oxide layer. See Figure 1.22 (f)
Step 6
The polysilicon layer structure is patterned by photomasking and
is etched. See Figure 1.22 (g)
Step 7
Formation of n-doped source and drain of the n-channel devices
in the p-islands. By the photoresist technique, the n-islands are
covered with an n-type dopant, usually phosphorus, is implanted.
The dopant will be blocked at the n-islands by the photoresist,
and it will be blocked from the gate region of the p-islands by the
polysilicon. See Figure 1.22 (h)
Step 8
Formation of p-doped source and drain of the p-channel devices in the n-islands. By the
photoresist technique the p-islands are covered with an p-type dopant, usually boron, is
implanted.
The dopant will be blocked at the p-islands by the photoresist, and it will be blocked from
the gate region of the n-islands by polysilicon. See Figure 1.22 (i)
Step 9
The above formed p-channel islands and n-channel islands are covered with an insulator
usually a layer of phosphorus glass or silicon-dioxide under high temperature.
Step 10
The glass is etched at contact-cut locations. The
metallization layer is formed next b, evaporating
aluminum over the entire surface and etching it
to leave only the desired metal wires.
The aluminum will flow through the contact
cuts to make contact with the diffusion or
polysilicon regions. See Figure 1.22 (j)
Step 11
A final passivation layer of phosphorus glass is
deposited and etched over bonding pad
locations.
The Advantages of SO1 Technology
Due to the absence of wells, transistor structures denser than bulk silicon
are feasible.
Also direct n-to-p connections may be made.
Lower substrate capacitances provide the possibility for faster circuits.
No field-inversion problems exist (insulating substrate).
There is no latch-up because of the isolation of the n and p-transistors by
the insulating substrate. Because there is no conducting substrate, there
are no body-effect problems.
There is enhanced radiation tolerance (This is almost the sole reason the
technology has been justified to date).
The Disadvantages of SOI Technology
The absence of a backside substrate contact could lead to odd device
characteristics.
Such as the "kink" effect in which the drain current increases abruptly at
around 2 to 3 volts.
