OCC Circuit Design for Clock Control
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chaitanyaOCC Circuit Design for Clock Control
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Powered by AIDuring stuck-at testing, the OCC ensures that only one clock pulse is generated in the capture phase by using its internal PLL to produce a steady and precise clock signal. This design guarantees synchronization with the functional clock's frequency and prevents any extraneous clock signals during critical test phases .
To enable the slow clock, the slow_clock_enable signal must be set to '1', and PLL_bypass to '0'. This sequence of operations results in the output of the initial OR gate being '1'. Subsequently, the output of the second OR gate is also '1' when one input is PLL_bypass being '0' and another input is scan_enable being '1'. All three inputs to the AND gate must be '1', which enables the slow clock by engaging the final output logic .
The OCC manages transitions from scan operation mode to functional mode by bypassing the test clock in a scan-friendly design. It transitions to enabling the functional clock by coordinating signal conditions—specifically manipulating PLL_bypass and enable settings—to shift from testing pulse control back to the functional phase, permitting normal operation .
The fast clock is enabled during at-speed testing by setting the fast_clk_enable to '1' and PLL_bypass to '0'. The output of the first AND gate is driven to '1', powered by logical conjunctions in the gate network, with subsequent NAND gates ensuring the necessary states are achieved to result in a final activation output to the main OR gate, completing the circuit for fast clock enablement .
To enable the fast clock, the OCC requires fast_clk_enable to be '1' and PLL_bypass to be '0', resulting in the activation of the fast clock via a logical circuit involving AND and NAND gates. Conversely, to enable the slow clock, slow_clock_enable needs to be '1', and similarly, PLL_bypass to be '0'. This configuration routes the clock through OR and AND logic gates, resulting in enabling the slow clock .
The internal PLL clock within the OCC is significant because it generates precise test clock pulses necessary for both stuck-at and at-speed testing. By avoiding dependence on external I/O frequency limitations, it facilitates accurate synchronization with the functional clock, ensuring reliable capture phases and controllable test conditions without overstressing the system .
The OCC uses a combination of test mode and PLL settings to determine clock activation. When test mode is set to 1, the fast clock (PLL) is enabled, providing two clock pulses for at-speed testing. Conversely, when PLL_bypass is '0' and test mode is '0', the OCC bypasses this, enabling the slow or functional clock, ensuring the test clock aligns correctly with the designed requirements .
The On-chip Clock Controller (OCC) is crucial during silicon testing on Automatic Test Equipment (ATE) as it controls clocks required for testing. It generates clock pulses using an internal PLL clock, managing the frequency limitations of I/O pads by routing test clocks through the OCC instead. During stuck-at testing, it ensures a single clock pulse in the capture phase, and for at-speed testing, it manages two clock pulses matching the functional clock frequency .
A free-running clock is used during EXTEST mode to facilitate testing of external logic circuits by keeping the system's clock running without interruption. In this mode, the OCC of Block 'A' operates as it normally would, allowing constant clock output, while Block 'B' remains in a transparent state to buffer and manage data flow .
In INTEST mode, each OCC within blocks controls the internal logic check, with Block 'A' remaining in a transparent mode to enable a free-running clock for Block 'B'. In contrast, in EXTEST mode, Block 'A' operates normally while Block 'B' buffers, engaging input wrapper cells for shift and capture operations. Here, the OCC in Block 'A' manages external logic tests with a free-running clock, simultaneously maintaining transparency for Block 'B' .