Digital Electronics

Sequential Logic Circuit Design

Sequential Logic Circuits
 Any sequential logic system can be broken down into two sections:
 Memory part
 combinational part

 The combinational part will comprise the usual AND, OR gates etc.
 The memory part is usually implemented with bistable devices.
 Two basic types: latches and flip-flops.
 Sequential Logic Circuits
 Any sequential logic system can be
broken down into two sections:
 Memory part
 combinational part INPUTS OUTPUTS
 COMBINATIONAL
LOGIC
 The combinational part will comprise
the usual AND, OR gates etc.
 The memory part is usually
MEMORY
implemented with bistable devices.
 Two basic types: latches and flip-
flops. CLOCK
 A latch changes state when the input states change. This property
is known as transparency. Data is stored by the latch when an
enable input (if provided) is valid.

 A flip-flop however can only change state on the application of a
clock pulse.
 A purely sequential system is one in which the output is
determined by the order in which the input signals are applied.
 Sequential circuits are classified as asynchronous (unclocked) or
synchronous (clocked).
 The Basic Latch
 The basic latch has two A
X
stable states that Truth table as shown below:
correspond to a logic 1
Y
and logic 0. The output B

changes from one state

to another depending on
A B X Y
the inputs.
0 0 1 1
 Consider the simple latch 0 1 1 0

shown below. 1 0 0 1
1 1 X X
  This is the basis of the SR (or RS) latch ,
This is the basis of the SR (or RS) latch , where A=R, B=S, X=Q and Y=/Q. The circuit symbol is shown below.

where A=S, B=R, X=Q and Y=/Q. The

circuit symbol is shown below.
S Q

R Q
 The Gated SR Latch
S A
 X
Q

CLOCK

Q
R B Y

CLK

with a waveform diagram as

Q shown below.

Q
 Gated SR Latch

 Often it is desirable to use a special control signal to inhibit state

changes in an SR latch while S and R are changing.
 This device is commonly referred to as a gated SR latch, since the
control signal can be thought of as opening a gate through which
signals on the S and R inputs propagate to the output.
 Circuit Structure: In Fig. 6.13a, a control signal C, is added to an
SR latch to apply the inputs S and R.
 The two AND gates apply the control signal S and R during time
intervals when the enable signal C is logic 1.
 When C is logic 0, the inputs are held in the S = R = 0 state.
 Gated SR Latch (continued)

 So the operation of the latch is as follows:

 when C = 0, no change occurs
 when C = 1, the SR excitation table of Fig. 6.11a and the
characteristic equation describe its function.
 If the AND gates are changed to NAND gates and cross-coupled
NAND gates are used for the SR latch, the circuit of Fig. 6.13b
results.
 The NAND gate implementation of the gated SR latch is shown in Fig.
613.c.
 The generic logic symbol for the gated SR latch is shown in Fig. 6.13d.
 Figure 6.13
Gated SR Latch
S S
S Q S Q

C C

R Q R Q
R R

(a) (b ) With NAND SR latch

With NOR SR latch

S S Q
C S Q
C
C

Q R Q
R C R
(c)
NAND logic diagram
(d) logic symbol
 Gated SR Latch (continued)

 Characteristic Equation: The complete excitation table and state

diagram of the gated SR latch are given in Figs. 6.14a and b.
 From the excitation table the characteristic equation is derived:
Q* = SC + RQ + CQ
 Note that when C = 0 this equation reduces to Q* = Q which
means that the present state is held.
 When C = 1 the equation becomes: Q* = S + RQ, the
characteristic equation of the simple SR latch, and thus the latch
is enabled.
 Gated SR Latch Characteristics

E n ab le E xcitation P resen t N ext

in p u ts in p u ts state
state
C S R Q Q*
0   0 0 H old
0   1 1
1 0 0 0 0
N o ch an ge
1 0 0 1 1
1 0 1 0 0 R eset
1 0 1 1 0
1 1 0 0 1 S et
1 1 0 1 1
1 1 1 0  N ot allow ed CSR
1 1 1 1  0dd, 10d 0dd, 1d0
(a)
110
Excitation table
0 1
101
(b )
State diagram

Figure 6.14
The truth table is now:

 The truth table is now: R S Cl

k
Q /
Q

X X 0 X X Same as A
 Symbol =B=1
0 0 1 X X Same as A
=B=1
0 1 1 1 0
S
Q
1 0 1 0 1
CK
1 1 1 1 1
Q
The function of the RS
R gated latch can be illustrated with a waveform diagram as shown below.
 The JK Flip-Flop

 The JK flip-flop is basically an SR gated latch

with modifications to eliminate the problems of
the final indeterminate state. When the two
inputs J and K are both 1 then the output Q
changes state. It is said to toggle under these
conditions. J
Q

 Circuit Symbol: CK

Q
 K
J K Qn+1

0 0 Qn

0 1 0

1 0 1

1 1 /Qn
 The D-Type Flip-Flop
D J
Q
 The D (data) type flip- CK

flop is basically a single- CK

K
Q

bit storage device. It can

be constructed by
connecting an inverter
between the J and K D Qn+
1

inputs of a JK flip-flop as 0 0
1 1
shown overleaf.
 Data appearing on D Q

the data input D is CK

simply clocked Q

through to the output

Q on the application
of a clock pulse.
 Symbol:
 Delay Latch

 When storing data, a memory element’s excitation input is simply the

data to be stored.
 A device (which is called a delay latch or D latch) is needed that
transfers a logic value on its excitation input D into the cross-coupled
storage cell of a latch.
 The logic symbol of the D latch is shown in Fig. 6.15a. Such a device
can be created from a gated SR latch, by assigning S = D and R = D.
 The D latch excitation table and state diagram is shown in Figs. 6.16 a
and b.
 A NAND implementation of the D latch is shown in 6.15b and NOR is
shown in 6.15c.
 D Latch Characteristics

E n ab le E xcitation P resen t N ext

in p u t in p u t state state

C D Q Q*
0  0 0 H old
0  1 1
1 0 0 0 S tore 0
1 0 1 0
1 1 0 1
S tore 1
1 1 1 1
(a) Excitation table
CD
0d, 10 0d, 11
11
0 1
10

(b )

State diagram
Figure 6.16
 D Latch (continued)

 Characteristic equation: this equation can be derived from that of

the gated SR latch by substituting D for S and D for R: Q* = DC +
CQ (= SC + RQ + CQ)=(DC+DQ+CQ)=(DC+CQ))

 When the enable signal is low, (C = 0), the equation reduces to

Q* = Q, meaning the latch is placed in hold mode (no change)
operating mode with the latch holding the last value of D that was
entered.
 When the enable signal is high (C = 1), Q* = D, the excitation input
D is gated directly to output Q (gated or enabled mode).
 Fig. 6.17 illustrates the timing diagram for D latch operation.
 D Latch Timing Diagram

E n ab led E n ab led
E n ab led
H old
H old

Figure 6.17
 D Latch (continued)

 Timing Constraints : To ensure that a specific value on excitation

input D will determine the final state of the latch, D must not be
allowed to change too near the time at which the enable signal
makes its transition from high to low.
 Set up time: denoted tsu
is defined as the period of time immediately preceding the enable
signal transition during which the excitation input must be stable.
 That is, the excitation input must be set up at least t su prior to the
enable signal transition and should not change until well after the
transition.
 D Latch (continued)

 Hold time : denoted th

is defined as the period of time immediately following the enable signal
transition during which D should not change. Therefore, the excitation
input must be held constant for at least th following the enable signal
transition to ensure the correct value has been latched.
 Setup and hold times are illustrated in Fig. 6.18
 Note the two constraint violations:
- the change in D from 0 to 1 too close to the clock edge represents a
setup time violation
- the change in D from 1 to 0 too soon after the clock edge may result in
an unpredictable state.
 The T-Type Flip-Flop
T J
Q
 The T (toggle) type flip- CK

flop also has a single CK

K
Q

input. It too can be

implemented using a JK T Qn+1

flip-flop; the inputs are 0 Qn

simply connected 1 /Qn

together as shown below

 PR
 PR ESET and Clear J
Q

CK
inputs K
Q
CL

 Positive and negative

edged triggered devices CK CK
 Table 6.3
Summary of Latch and Flip-Flop Characteristics

Device Characteristic Equation

SR latch Q* = S + RQ
Gated SR latch Q* = SC +QR + CQ
D latch Q* = DC + CQ
SR flip-flop Q* = S + RQ
D flip-flop Q* = D
JK flip-flop Q* = KQ + JQ
T flip-flop (edge-triggered) Q* = Q
T flip-flop (clocked) Q* = TQ + TQ
 Flip-Flops

 The latch circuits presented thus far are not appropriate for use in
synchronous sequential logic circuits.
 The possibility of two cascaded combinational circuits feeding
each other, generating oscillations and unstable transient behavior
can be controlled by using a special timing control signal called a
clock.
 The clock can then be used to restrict the times at which the states
of the memory elements may change thus preventing the unstable
behavior just described.
 Master-Slave SR Flip-Flops

 One method to prevent unstable behavior is to employ two latches

in a master-slave configuration as shown in Fig. 6.21a.
 When the clock signal C is low, the master latch is in the gated
mode and slave is in the hold mode. Changes on the excitation
input signal S and R are gated into the master latch while the
slave latch ignores any changes on its inputs.
 When the clock changes to logic 1, the two latches exchange roles.
The slave latch enters the gated mode, sending the output of the
master latch to the flip-flop output Q, while the master latch
enters the hold mode.
 Master-Slave SR Flip-Flops (continued)

 Master-slave flip-flops are sometimes called pulse triggered because

they require both logic 0 to 1 and 1 to 0 transitions on the clock
input in order to operate properly.
 The logic symbol of Fig. 6.21b indicates the pulse-triggered nature
of the device by showing the clock edge transition that enables the
slave at the flip-flop output terminals Q and Q.
 In Fig. 6.21b, the rising transition indicates that the flip-flop outputs
change on the positive edge of a pulse on the clock signal.
 If the SR flip-flop is used in a synchronous sequential circuit, an
unstable oscillation cannot occur because, at all times, either the
master or the slave latch is in the hold mode (Fig. 6.21d).
 Master-slave SR flip-flop

M aster S lave
QM
S S Q S Q Q
C C
R R Q R Q Q

C
(clock )

(a) Logic diagram S Q

C
R Q
(b) Pulse-triggered device logic symbol
Figure 6.21
 Master-slave SR flip-flop (continued)

M aster g a te d ho ld g a te d ho ld g a te d ho ld g a te d ho ld

S lave ho ld g a te d ho ld g a te d ho ld g a te d ho ld g a te d

S
R

QM
Q S an d R m ay
n ot ch an ge

R
Flip -flop ou tp u t can
ch an ge S
( c) Timing behavior t su
(setu p )
C
th
(h old )
tw tw
C low p u lse w id th C h igh p u lse w id th
(m aster en ab led ) (slave en ab led )
(d) Timing constraints
Figure 6.21
 Excitation Table and Characteristic Equation

 The excitation table and state diagram for the SR master-slave

flip-flop are presented in Figs. 6.22a and b.
 Note that the columns S, R, and Q denote the conditions on the
flip-flop signals before the clock pulse is applied.
 The Q* column denotes the flip-flop output after the clock pulse
has been applied.
 The state diagrams of the simple SR latch and the master-slave SR
latch are identical. The difference between them is that the latch
changes states immediately when S or R changes, whereas all flip-
flop state changes are triggered by clock pulses.
 SR Master-Slave Flip-Flop Characteristics

S R Q C Q*
0 0 0 0 N o ch a n g e
0d SR 0d
0 0 1 1
0 1 0 0 R eset 10
0 1 1 0 0 1
1 0 0 1 S et 01
1 0 1 1
(b )
1 1 0  N o t a llo w ed
1 1 1 
(a )

Q* = S + RQ

Figure 6.22
 Master-Slave D Flip-Flops

 A master-slave D flip-flop can be built from two D latches as shown in Fig.

6.23a.
 This flip-flop operates in the same manner as the SR version; the master
latch is gated when the clock is low and the slave, when the clock is high.
 The logic symbol for this pulse-triggered device indicates that the outputs
change on the positive edge of a pulse on the clock signal (Fig. 6.23b).
 The overall behavior of the D flip-flop output Q can be summarized by
noting that Q will assume the value of D on the rising edge of the clock C.
 Therefore, the characteristic equation for a master-slave D flip-flop is :
Q* = D
 Master-Slave D Flip-Flop

M aster S lave
QM
D D Q D Q Q

D Q
C Q C Q Q

C Q
C
(clock ) (b )
(a)

Figure 6.23
 Master-slave D flip-flop characteristics

D Q C Q*
0 D 1
0 0 0 1
S tore 0
0 1 0  
1 0 1
S tore 1 0
1 1 1

E n ab led : M S M S M S M S M

QM

Q = QS

Figure 6.24
 Master-Slave JK Flip-Flops

 The JK operates as an SR flip-flop whose inputs are assigned J = S and

K = R.
 However, whereas the S = R = 1 combination is not allowed, the JK
uses this special case to incorporate a very useful mode of operation.
 The additional feature of the JK device is that it state toggles, that is
changes from 0 to 1 or from 1 to 0 when J = K = 1.
 Examination of the state diagram, shown in Fig. 6.25b, indicates that
the JK flip-flop will change from the 0 state to the 1 state with an input
of J = 1 and K = 0 or J = 1 and K = 1 (toggle).
 This means that a logic 1 on J will force the device into the 1 condition
no matter what value is placed on K. So K is a don’t-care in this case.
 Pulse-triggered JK flip-flop characteristics

J K Q C Q*
0 0 0 0 H old 0d JK d0
0 0 1 1
0 1 0 0 R eset 1d
0 1 1 0
0 1
1 0 0 1 S et
1 0 1 1 d1
1 1 0 1
1 1 1 0 T oggle (b) State diagram

(a) Excitation table

JK J
Q 00 01 11 10

0 0 0 1 1

Q 1 1 0 0 1

Figure 6.25 K
( c) K-map for Q*
 JK Flip-Flops (continued)

 By plotting the next state Q* on a K-map, as shown in Fig 6.25c,

the characteristic equation of the JK flip-flop can be derived:
Q* = KQ + JQ
 From this equation, the logic diagram for the flip-flop can be
derived as presented in Fig. 6.26a.
 The logic symbol for this device is shown in Fig. 6.26 b. Note that
the clock input signal is inverted within the device itself so that the
slave will change on the falling edge of the clock.
 Main Points

 Sequential Logic Circuits.

 Latch
 J-K flip-flop
 D – Type flip-flop
 T-type flip-flop
 Counters
 Shift register
 Behavioral Modeling

There are two kinds of behavioral statements in Verilog HDL:

initial and always.

initial initial
begin begin
clock = 1`b0; clock = 1`b0;
repeat (30) #300 $finish;
#10 clock = ~clock; end
end always
#10 clock = ~clock;
41
 Behavioral Modeling

The always statement can be controlled by delays that wait

for a certain time or by certain conditions to become true or
by events to occur.

always @(event control expression)

procedural assignment statements.

always @(A or B or Reset)

always @(posedge clock or negedge reset)

42
 Flip-Flops and Latches

HDL Example 5-1

//Description of D latch (See Fig. 5-6)

module D_latch (Q, D, control);
output Q;
input D, control;
reg Q;
always @(control or D)
if (control) Q = D; //Same as: if (control ==1)
endmodule

43
 Flip-Flops and Latches
HDL Example 5-2
//D flip-flop
module D_FF (Q, D, CLK);
output Q;
input D, CLK;
reg Q;
always @(posedge CLK)
Q = D;
endmodule

// D flip-flop with asynchronous reset.

module DFF (Q, D, CLK, RST);
output Q;
input D, CLK, RST;
reg Q;
always @(posedge CLK or negedge RST)
if (~RST) Q = 1`b0; // Same as: if (RST ==0)
else Q = D;
endmodule
44
 Flip-Flops and Latches
HDL Example 5-3
//T flip-flop from D flip-flop and gates
module TFF (Q, T, CLK, RST);
output Q;
input T, CLK, RST;
reg DT;
assign DT = Q ^ T;
//Instantiate the D flip-flop
DFF TF1 (Q, DT, CLK, RST);
Endmodule

// JK flip-flop from D flip-flop and gates

module JKFF (Q, J, K, CLK, RST);
output Q;
input J, K, CLK, RST;
wire JK;
assign JK = (J & ~Q) | (~K & Q);
// Instantiate D flipflop
DFF JK1 (Q, JK, CLK, RST);
endmodule 45
 Flip-Flops and Latches
HDL Example 5-4
// Functional description of JK flip-flop
module JK_FF (J, K, CLK, Q, Qnot);
output Q, Qnot;
input J, K, CLK;
reg Q;
assign Qnot = ~Q;
always @ (posedge CLK)
case ({J, K})
2`b00: Q = Q;
2`b01: Q = 1`b0;
2`b10: Q = 1`b1;
2`b11: Q = ~Q;
endcase
endmodule
46
 Registers
When a set of n flip-flops is used to store n bits of information, such as
an n-bit number, we refer to these flip-flops as a register.
A register that provides the ability to shift its contents is called a shift
register.
Figure shows a four-bit shift register that is used to shift its contents one
bit position to the right.
The data bits are loaded into the shift register in a serial fashion using
the In input.
The contents of each flip-flop are transferred to the next flip-flop at
each
positive edge of the clock.
An illustration of the transfer is given in Figure 7.18b, which shows
what happens when the signal values at In during eight consecutive
clock cycles are 1, 0, 1, 1, 1, 0, 0, and 0, assuming that the initial state 47
48
 Parallel Access Shift Register

49
 Transmitting all bits at once using n separate wires, in which case we
say that the transfer is performed in parallel.
But it is also possible to transfer all bits using a single wire, by
performing the transfer one bit at a time, in n consecutive clock cycles.
We refer to this scheme as serial transfer. To transfer an n-bit data item
serially, we can use a shift register that can be loaded with all n bits in
parallel (in one clock cycle).
Then during the next n clock cycles, the contents of the register can be
shifted out for serial transfer.
The reverse operation is also needed. If bits are received serially, then
after n clock cycles the contents of the register can be accessed in
parallel as an n-bit item.

50
51
 In Figure 7.19 we have chosen to label the
flip-flops outputs as Q3, . . . ,Q0 because
 shift registers are often used to hold binary
numbers. The contents of the register can be
 accessed in parallel by observing the outputs
of all flip-flops. The flip-flops can also be
 accessed serially, by observing the values of
Q0 during consecutive clock cycles while the
contents are being shifted.
52
 A circuit in which data can be loaded in series
and then accessed
 in parallel is called a series-to-parallel
converter. Similarly, the opposite type of
circuit is a
 parallel-to-series converter. The circuit in
Figure 7.19 can perform both of these
functions.

53
 The End

 Thank you for your

attention.