VLSI Design

21EC63

Dept. of ECE
Module 3 Abhilash G.
Dept. of ECE Abhilash G.
Semiconductor Memories

CSP.
Assistant Professor,
Department of ECE,

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 Module-5
Memory and Testing
• Semiconductor Memories: Introduction,
Dynamic Random Access Memory (DRAM) and
Static Random-Access Memory (SRAM),
Nonvolatile Memory, Flash Memory, Ferroelectric
Random Access
• Memory (FRAM) (10.1 to 10.6 of TEXT1)
TEXT1. “CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo
Kang & Yosuf Leblebici, Third Edition, Tata McGraw-Hill.
TEXT2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E.
Weste, and David Money Harris, 4th Edition, Pearson Education.

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 Course Outcomes
After studying this course, students will be able to:
• Demonstrate understanding of MOS transistor theory, CMOS
fabrication flow and technology scaling.
• Draw the basic gates using the stick and layout diagrams with the
knowledge of physical design aspects.
• Demonstrate ability to design Combinational, sequential and
dynamic logic circuits as per the requirements
• Interpret Memory elements along with timing considerations
• Interpret testing and testability issues in VLSI Design

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 Semiconductor Memories

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 Overview of semiconductor memory types

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 Typical random-access memory array organization.

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Read-Only Memory (ROM) Circuits (4 bit X 4 bit NOR based)

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 Layout example of a NOR ROM array.

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 Layout of the 4-bit x 4-bit NOR ROM

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 4-bit x 4-bit NOR ROM

Arrangement of the nMOS

transistors in the implant-mask
programmable NOR ROM array.
Every metal-to-diffusion contact is
shared by two adjacent devices.

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 4-bit x 4-bit NOR ROM

Layout of the 4-bit x 4-bit NOR ROM array.

The threshold voltages of “1” -bit transistors
are raised above VDD through implant.

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 4-bit x 4-bit NAND-based ROM array

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 4-bit x 4-bit NAND-based ROM array

Implant-mask layout of the NAND ROM array.

The threshold voltages of “0”-bit transistors are
lowered below 0 V through implant.

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 Design of Row and Column Decoders

Row address decoder example for 2 address bits and 4 word lines.

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 NOR-based decoder array

NOR-based row decoder circuit for 2

address bits and 4 word lines.

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 NOR-based and
NAND-based decoder array

NAND ROM array, and implementation of the row decoder

circuit and the ROM array as two adjacent NAND planes.

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 NOR-based decoder array

Bit-line (column) decoder

arrangement using a NOR address
decoder and nMOS pass transistors
for every bit line.

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 NOR-based decoder array

Column decoder circuit for eight bit lines,

implemented as a binary tree decoder which is
driven directly by the three column address bits.

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 Static Read-Write Memory (SRAM) Circuits

(a) Symbolic representation of the (b) Generic circuit topology of the

two-inverter latch circuit with MOS static RAM cell.
access switches.

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 Static Read-Write Memory (SRAM) Circuits

(c) Resistive-load SRAM cell. (d) Depletion-load nMOS SRAM cell. (e) Full CMOS SRAM cell

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 SRAM Operation Principles

Basic structure of the

resistive-load SRAM cell,
shown with the column
pull-up transistors.

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 SRAM Operation Principles
Write "1" operation:

C to logic-low by the data-write circuitry -> M1 turns off.

V1 = logic-high level
V2= logic-low level.

Read "1" operation:

C retains its pre-charge level

C is pulled down by M2 and M4.
Data-read circuitry detects the small voltage difference (V >
VZc)
Amplifies it as a logic "1" data output.

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 SRAM Operation Principles
Write "0" operation:

C is forced to logic-low by the data-write circuitry.

Driver transistor M2 turns off.
Voltage V2 attains logic-high level
V1 goes low.
Read "0" operation

C retains pre-charge level

C pulled down by M1 and M3.
small voltage difference (Vc < VE)
Amplifies it as a logic "0" data output

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 SRAM Operation Principles

Typical row and column voltage waveforms of the resistive-load

SRAM shown in Fig. 10.22 during read and write.

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 Full CMOS SRAM Cell

Circuit topology of the CMOS SRAM cell

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 CMOS SRAM Cell Design Strategy

Layout of the resistive-load SRAM cell. Layout of the CMOS SRAM cell.

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 CMOS SRAM Cell Design Strategy

Layout of a 4-bit x 4-bit SRAM array, consisting

of 16 CMOS SRAM cells.

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 CMOS SRAM Cell Design Strategy

Voltage levels in the SRAM cell at the beginning

of the "read" operation.

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 CMOS SRAM Cell Design Strategy

Voltage levels in the SRAM cell at the beginning

of the "write" operation.

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 SRAM Write Circuitry

Data write circuitry associated with one

column-pair in an SRAM array.

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 Fast Sense Amplifiers

Differential current-mirror amplifier to

speed up the memory read access time.

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 Fast Sense Amplifiers

Two-stage differential current-mirror sense

amplifier circuit.

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 Fast Sense Amplifiers

Cross-coupled nMOS sense amplifier circuit.

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 Dual-Port Static RAM Arrays

Complete circuit diagram of a CMOS static RAM column

with data write and data read circuitry.

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 Dual-Port Static RAM Arrays

Circuit diagram of the CMOS dual-port SRAM cell.

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 Testing and Verification

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 Manufacturing Test
• A speck of dust on a wafer is sufficient to kill chip
• Yield of any chip is < 100%
• Must test chips after manufacturing before delivery to customers to only
ship good parts
• Manufacturing testers are
• very expensive
• Minimize time on tester
• Careful selection of
• test vectors

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 Manufacturing Failures

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 Stuck-At Faults
• How does a chip fail?
• Usually failures are shorts between two conductors or opens in a conductor
• This can cause very complicated behavior
• A simpler model: Stuck-At
• Assume all failures cause nodes to be “stuck-at” 0 or 1, i.e. shorted to GND
or VDD
• Not quite true, but works well in practice

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 Examples

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 Observability & Controllability
• Observability: ease of observing a node by watching external output pins
of the chip
• Controllability: ease of forcing a node to 0 or 1 by driving input pins of the
chip

• Combinational logic is usually easy to observe and control

• Finite state machines can be very difficult, requiring many cycles to enter
desired state
• Especially if state transition diagram is not known to the test engineer

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 Test Pattern Generation
• Manufacturing test ideally would check every node in the circuit to prove it is
not stuck.
• Apply the smallest sequence of test vectors necessary to prove each node is not
stuck.

• Good observability and controllability reduces number of test vectors required

for manufacturing test.

• Reduces the cost of testing

• Motivates design-for-test

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 Test Example
SA1 SA0
• A3 {0110} {1110}
• A2 {1010} {1110}
• A1 {0100} {0110}
A3 n1
• A0 {0110} {0111} A2
Y
• n1 {1110} {0110} n2 n3
A1
• n2 {0110} {0100} A0
• n3 {0101} {0110}
• Y {0110} {1110}

• Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}

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 Design for Test
• Design the chip to increase observability and controllability

• If each register could be observed and controlled, test problem

reduces to testing combinational logic between registers.

• Better yet, logic blocks could enter test mode where they generate
test patterns and report the results automatically.

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 Scan
CLK
• Convert each flip-flop to a scan register SCAN

Flop
SI
• Only costs one extra multiplexer D
Q

• Normal mode: flip-flops behave as usual

• Scan mode: flip-flops behave as shift register
scan-in

Flop

Flop

Flop
• Contents of flops

Flop

Flop

Flop
• can be scanned inputs
Logic
Cloud
Logic
Cloud outputs

Flop

Flop

Flop
• out and new

Flop

Flop

Flop
• values scanned
• in
scanout

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 Scannable Flip-flops

SCAN
SCAN CLK Q
 
D
D 0 X

Flop
Q Q
SI 1 SI  
(a)  

(b)
 

d

 D
 Q
d
SCAN
d X
Q
s  
s 
SI
(c)
s
 

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 ATPG
• Test pattern generation is tedious

• Automatic Test Pattern Generation (ATPG) tools produce a good set of vectors
for each block of combinational logic

• Scan chains are used to control and observe the blocks

• Complete coverage requires a large number of vectors, raising the cost of test

• Most products settle for covering 90+% of potential stuck-at faults

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 Built-in Self-test

• Built-in self-test lets blocks test themselves

• Generate pseudo-random inputs to comb. logic

• Combine outputs into a syndrome

• With high probability, block is fault-free if it produces the expected syndrome

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 PRSG
• Linear Feedback Shift Register
• Shift register with input taken from XOR of state
• Pseudo-Random Sequence Generator
Step Y
CLK Y 0 111
Q[0] Q[1] Q[2]
Flop

Flop

Flop
D D D
1 110
2 101
3 010
Flops reset to 111 4 100
5 001
6 011
7 111 (repeats)

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 BILBO
• Built-in Logic Block Observer
• Combine scan with PRSG & signature analysis
D[0] D[1] D[2]

C[0]
C[1]

Q[2] / SO

Flop

Flop

Flop
SI 1

0 Q[0]
Q[1]

MODE C[1] C[0]

Scan 0 0
Logic Signature
PRSG Test 0 1
Cloud Analyzer
Reset 1 0
Normal 1 1

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