Module 3
• Semiconductor Memories: Introduction, Dynamic Random Access
Memory (DRAM) and Static Random Access Memory (SRAM),
Nonvolatile Memory, Flash Memory, Ferroelectric Random Access
Memory (FRAM) (10.1 to 10.6 ofTEXT2)
• The area efficiency of the memory array, i.e., the number of stored data bits per unit area, is one of
the key design criteria that determine the overall storage capacity and, hence, the memory cost per
bit.
• The memory access time, which is the time required to store and/or retrieve a particular data bit in
the memory array. The access time determines the memory speed, which is an important
performance criterion of the memory array.
• The static and dynamic power consumption of the memory array is a significant factor to be
considered in the design.
• The semiconductor memory is generally classified according to the type of data storage and data
access. Read/write (R/W) memory must permit the modification(Writing) of data bits stored in the
memory array, as well as their retrieval (reading)on demand.
Random Access Memory(RAM)
• The read/write memory is called Random Access Memory(RAM), in which any
cell can be accessed with nearly equal access time.
• The stored data is volatile that is the stored data is lost when the power supply
voltage is turned off.
• Based on the operation type of individual data storage cells, RAMs are classified
into two main categories. Dynamic RAMs (DRAM) and Static RAMs (SRAM).
• .
DRAM • The DRAM cell consists of a capacitor to store binary information, 1
(high voltage) or (low voltage), and a transistor to access the
capacitor. Cell information (voltage ) degraded mostly due to
junction leakage current at the storage node. Therefore the cell data
must be read and rewritten periodically (refresh operation)
• Due to low cost and high density, DRAM is widely used for the main
memory in personal and mainframe computers, and engineering
workstations.
• The DRAM cell consists of a capacitor and a switch transistor. The
data are stored in the capacitors. The presence of charge in the
capacitor is considered data "1" while the absence of charge in the
capacitor is data "0". The stored cha is subject to gradual decay due
to leakage current, thus refresh operation is required.
SRAM • The SRAM cell consists of a latch, therefore, the cell
data is kept as long as the power is turned on and
refresh operation is not required.
• SRAM is mainly used for the cache memory in
microprocessors, mainframe computers, engineering
workstations, and memory in hand-held devices due
to high speed and low power consumption.
• The SRAM cell has a six-transistor latch structure to
hold the state of each cell node. Since the cell data
can be held indefinitely at one of the two possible
states of the bistable latch as long as power supply is
provided, the refresh operation is not needed in
SRAMs.
Ferro-electric Random Access Memory
(FRAM)
• The FRAM cell has a similar structure to that
of DRAM except the ferroelectric capacitor,
where the cell data are modified by changing
the polarization of ferroelectric material.
• Ferro-electric Random Access Memory
(FRAM) is a type of
Random Access Memory, which uses a ferro-
electric capacitor to achieve it’s non-volatility
(content is not lost when power is turned off).
Read-Only Memory (ROM)
• Read-Only Memory (ROM) allows, only retrieval of previously stored data and does not permit
modifications of the stored information contents during normal operation.
• ROMs are nonvolatile memories, that is the stored data is not lost even when the power supply is
off and refresh operation is not required.
• Depending on the type of data storage (data writing) method, ROMs are categorized as
Mask ROM, in which data are written during chip fabrication by using a photo mask and
programmable ROM.
Depending on data erasing characteristics, PROMs are further classified into Fuse ROM,
Erasable PROM (EPROM) and Electrically Erasable PROM (EEPROM).
• .
The data written by blowing the fuse electrically cannot be erased and modified in Fuse
ROM.
Data in EPROMs and EEPROMs can be rewritten, but the number of subsequent re-write
operations is limited.
In EPROMs, ultraviolet rays that can penetrate through the crystal glass on the package are used to
erase whole data in the chip simultaneously, while high electrical voltage is used to erase data in
EEPROMs.
Flash memory is similar to EEPROM, where data can be erased by using a high electrical voltage.
A drawback of EEPROM is the slower write speed, in the order of microseconds.
In Mask (Fuse) ROM, the data are programmed by a Mask pattern (blowing the fuse located at
each cell, thereby cutting the electrical connection of the corresponding device). Only one-time
programming operation is allowed.
Flash memory
• The signal levels at the inside and outside of the memory array are different. (the
Transistor-Transistor Logic (TTL) signal on the memory board and CMOS signal in the
memory chip) the level of addresses is converted through the memory chip interface,
called input address buffers.
• The row and column selection operations are accomplished by row and column
decoders.
• The row decoder circuit selects one out of 2N word lines according to an N-bit row
address and the column decoder circuit selects one out of 2M bit lines according to an
M-bit column address.
• Once a memory cell or a group of memory cells is selected in this fashion. a data read or
write operation is performed on the selected single or multiple bits on a particular row.
• The column address serves the double duties of selecting the particular columns and
routing the corresponding data content in a selected row to the output through the
memory chip interface, called data row buffers.
• Chip Select (CS), Write Enable (WE) signals are used to activate the read or write
operation of the particular memory chip out of the memory cluster on the hoard.
• The data storage structure, or core, consists of individual memory cells arranged in an array of
horizontal rows and vertical columns.
• Each cell is capable of storing one bit of binary information.
• Each memory cell shares a common connection with the other cells in the same row, and another
common connection with the other cells in the same column.
• In this structure, there are 2N rows, also called word lines, and 2M columns, also called bit lines.
Thus, the total number of memory cells in this array is 2N x 2M.
• To access a particular memory cell, that is a particular data bit in this array, the corresponding
word line and the corresponding bit line must be activated (selected)according to the addresses
coming from the outside of the memory array. These addresses are provided by the memory
controller or the processor directly.
Operation of Three-Transistor DRAM Cell
Write “1”
Read “1”
Write “0”
Read “0”
Operation of One-Transistor DRAM Cell
Write operation
• The capacitor Cm will be charged and with Read/Write = 1 and Row Select = 1 If
the Read/Write line is provided with logic 1, Cm will be charged to logic 1 and if
the line is provided with logic 0 charge stored will be logic 0.
Read operation
• If logic 0 is stored in Cm and when Row select line is high M1 is ON. Then the
sense amplifier at the bit line will sense and give the output as logic 0.
• If logic 1 is stored in Cm and when Row select line is high M1 is ON, the logic 1
stored will begin to discharge as the path exists. The sense amplifier senses this
and this gives the output as logic 1
•The different phases are the precharge phase, access phase, sense phase and restore phase.
•The Precharge phase is a prerequisite for a row access operation. Access, sense and restore phases are
performed in sequence to the row access operation.
•In the precharge phase, the bit lines are precharged to a voltage level of Vdd/2.
•In the access phase the word line I made high. This turns on the access transistor and the selected storage
cells discharge their content to the respective bit lines. In the case of digital value 1, the charge-sharing
process minutely increases the voltage on the bit line, with BL=1 and BL bar=0, the sense amplifier with
turn on the respective transistor to keep BL and BL bar at 1 and 0 respectively.(BL= Vdd/2+ ΔV) and BL bar=
vdd/2) .
•The final phase is the restore and it illustrates that after the bit lines are driven to the respective max and
min voltage values, the bit line voltages now restore the charge in the storage capacitor through the access
transistor
• Reading the memory state from the 1T bit cell involves a charge sharing process
between the Cs and bit line capacitor Cbl.
• When logic 1 (VDD) is stored in Cs and if the Bit line is precharged to VDD/2, with
Wl0 high, M1 is on.
•
Since Cs potential is more than the Bit line voltage, current will flow from Cs to bit
line capacitor and the voltage across Cs will decrease. Eventually, Voltage at Cs and
Voltage at the bit line will be equal, and ΔV will increase voltage at the bit line.
•
Similarly if Logic 0 is stored in Cs the voltage at the bit line will decrease from the
original VDD/2 by ΔV .
•
Positive ΔV indicates the cell stores “1” and negative ΔV indicates the cell stores
“0” which will be detected by the sense amplifier
Bit line Sense Amplifier
A differential version of BL exists
called BLB that is used to sense BL
and increase the sensitivity
This line is also pre-charged to VDD/2
and provides an initial reference for
BL
A latch amplifier is used to detect the
differences between BL and BLB
Bit line Sense Amplifier
Control signals SA and SAB are
used to selectively amplify the
bit lines.
PSA and PSAB, control the
load transistors for the Sense
Amps.
These are typically turned on
sequentially to reduce the
amount of simultaneous
charge movement
Bit Line Sense Amplifiers & Read Amps
• The values, of BL and BLB, will
eventually reach 0 and VDD.
• The Values are then connected
to a Read Amp through switch
transistors (MNC1 & MNC2).
• The Column Select line turns
on the switch transistors.
•
• The Read Amp then converts
the BL and BLB signals into full
swing high drive strength
signals (Dout)
DRAM operation modes
• The row-falling edge of the address strobe (RAS) samples the address and starts the READ operation
mode.
• The row addresses are supplied into the address pins and then comes the row address strobe (RAS)
signal.
• Column addresses are not required until the row addresses are sent in and latched.
• The column addresses are applied into address pins and then latched in by the column address strobe
(CAS) signal.
• The address is captured at the falling edge of the RAS bar and CAS bar.
• The access time tRAS is the minimum time for the RAS signal to be low and tRC is the minimum READ
cycle time
• Various asynchronous DRAM read modes. (a) Single bit read.
DRAM Page mode read
In modified DRAM circuitry related to the DRA chip output interface, read frequency can be improved
further. Instead of capturing the column address at the falling edge of CAS, a new column address is
captured at the rising edge of CAS and the read data is maintained during CAS precharge time. This is called
EDO (Extended Data-Our) access mode.
In hyper page mode, also know as EDO mode, the time between two consecutive CAS activations is shorter
than in normal page mode Column addresses are transferred more quickly, access time is shortened
significantly (about 30%) providing higher transfer rates
Synchronous DRAM
• In the synchronous access mode, the data read frequency is improved with the use of the system clock to
schedule the operations
• Read latency is defined as the number of system clock cycles, typically 2 or 3.
• Since data is sent out with the system clock, the read frequency can be about 150-200 MHz for conventional
synchronous mode.
• To improve bandwidth, data are sent out at both edges of the system clock, resulting in an effective
bandwidth increase by a factor of 2, called DDR (Dual Data Rate).
• By using an improved chip interface, data read frequency can be improved further to 400-800 MHz (DDR).
The chip interface with a small signal swing and clock recovery scheme is used to maximize the frequency.
Inputs to control the chip are sent
Synchronous DRAM read modes. (a)
Synchronous mode read (four bit burst read).
Synchronous DRAM read modes (b) Serial
mode read.
Leakage Currents in DRAM Cells and Refresh Operation
Different leakage mechanisms contribute to the decay of charge at the cell and
total leakage current is expressed as.
where Isub is the leakage current through the cell access transistor,
Itunneling is the tunnelling current through a thin dielectric material
Ij the junction leakage current at the storage node,
Icell-to-cell the leakage current across the field oxide.
• Icell-to-Icell is usually negligible due to the thick field oxide.
• Since Isub is a strong function of the threshold voltage. Increasing the VSB of the access
transistor reduces this leakage component Isub
• As the thickness of dielectric material is reduced to increase the cell capacitance, the tunnelling
leakage current becomes a serious issue.
• When the minimum feature size is scaled-down Ij tends to take a smaller portion of the total
leakage current.
• Hence a periodic refresh operation is always required to compensate for the steady leakage of
charge from the storage nodes, and to ensure the conservation of data in the DRAM cells.
• t
DRAM refresh operation
• Refresh Rate. In traditional “asynchronous” DRAM, there are two
types of devices, one with a standard refresh rate (15.6 us), and the
other with an extended refresh rate (125 us).
ROR Refresh Mode
• In asynchronous DRAM, To perform a RAS ONLY REFRESH, a row
address is put on the address lines and then the RAS bar is dropped.
When RAS bar falls, that row will be refreshed and as long as the CAS
bar is held HIGH, the DQs will remain open. (See Figure 2.)
• RAS-only refresh is performed by asserting RAS with a row address to
be refreshed, and CAS remains de-asserted.
• The controller is responsible for managing the rows to refreshed.
CAS-Before-RAS (CBR) Mode
• CAS-Before-RAS (CBR) Refresh. In traditional “asynchronous” DRAM,
CBR refresh starts by first asserting CAS and then asserting only RAS.
There is no requirement of sending a row address because a device
has an internal counter that increments with each CBR command.
• BEFORE REFRESH, also known as CBR REFRESH,
• It is a frequently used method of refresh because it is easy to use and
offers the advantage of power savings.
• CBR refresh starts by first asserting CAS and then asserting only RAS..
• One refresh cycle will be performed each time RAS bar falls.
• WE bar must be held HIGH while RAS bar falls.
•.
• An internal counter which is initialized to a random count when the
device is powered up.
• Each time a CBR REFRESH is performed, the device refreshes a row
based on the counter, and then the counter is incremented.
• When CBR REFRESH is performed again, the next row is refreshed and
the counter is incremented.
• The counter will automatically wrap and continue when it reaches the
end of its count. There is no way to reset the counter.
• The user does not have to supply or keep track of row addresses
Self Refresh Mode
• In self-refresh mode the device internally generates refresh pulses
using a built-in analogue timer.
• When a device is in SR mode, all external I/O pins and clocks are
disabled and the device preserves data without any intervention from
the memory controller.
• SR is the lowest power mode for a DRAM device without losing data.
• Since the logic level of the memory system board (e.g .. TTL (0.8 V .. 2.0 V)) and
those of the memory chip (e.g .. CMOS) are different memory interface circuits
are required to convert logic level.
• Those circuits are called input and output buffers and are specific for different
logic· interfaces.
DRAM Output circuit
• Output buffer sends the read data to external devices such as, a memory con
troller or a processor.
• The output buffer converts a data CMOS level to a system logic level (cg .. TTL )
and need to drive a large capacitive load.
• Output, of several DRAM chips, is usually connected to the same data bus, line.
• The output buffer of any DRAM chip must keep a high-impedance ( H 1 Z) state
when the chip is not selected.
DRAM Decoder
DRAM Decoder
• To select a cell from a 2M, memory array. M address bits are needed when the address is multiplexed Since
using a decoder with M transistors in series is practically impossible. the memory decoding ·scheme is
composed of pre and main decoder.
• Address bits are grouped in 2 or 3 bits and decoded (PRAOI, PRA234, PRA561, and PRA89) first in the
decoder stage.
• Word line are required to have a high voltage (Vrr) for full data restoration. The output level of a
predecoder (PRAOI) is boosted by using a level shifter.
• The main decoder uses the predecoded outputs to produce the word selection signal and a self
bootstrapped driver is placed for transferring the boosted voltage to the highly capacitive word line
without signal degradation.
• When the main decoder is selected node A is discharged and becomes low. Node C is set to VDD-Vtn
• As the boosted signal (BPRAOI) arrives at the drain of MN2, node C is coupled to a higher level and the
increased signal is transferred to the word line without experiencing a voltage drop.
DRAM Decoder
V PP for full restoration
Output of predecoder boosted
by level shifter
Self-bootstrapped driver for
transferring to highly cap. without
signal degradation
Voltage of C when main
decoder is selected
VC VPP V VDD VTN CMN 2 VPP
CMN 2 Cparasitic
C
© CMOS Digital Integrated Circuits – 4th Edition 95
Voltage Sense Amplifiers
To detect signal difference on data lines
Current-mirror differential
Popular and good common-mode rejection ratio
Large area and large power consumption
Full CMOS latch type
High speed, small area and low power
Precharge signal required
operation cannot be reversed
Semilatch type
Between current-mirror type and full CMOS latch type
© CMOS Digital Integrated Circuits – 4th Edition 96
•(a) Differential-output current-mirror type, (b) pMOS latch
type, c) full CMOS latch type.
• Various kinds of sense amplifiers are used to detect a signal difference on data lines
such as Current-mirror differential, semi-latch, and full latch types.
• The cross-coupled differential amplifier is used to achieve high speed, low power
consumption, and small area penalty.
• In the full CMOS type, OUT and OUT bar are precharged by PSAE.
• When PSAE goes to high, the amplifier starts to amplify a signal difference. As a node
(A or B) is discharged, the other output (B) becomes isolated from the other input
signal (IN bar), the sensing speed can be accelerated, and power consumption can be
small.
• There is no static power consumption after the sensing is completed and can be used
in low power applications.
• However, a precharge signal (PSAE) is required and output nodes are precharged
properly before starting a new sensing operation.
• A valid signal difference must be guaranteed because its operation cannot be
reversed; that is, the states of output nodes cannot be reset once they are latched
until the next precharge signal arrives.
• Performance of the semilatch type sense amplifier is between that of the current-
mirror and that of the full CMOS latch type.
Internal Voltage Regulator
Circuit
Lowering voltage to reduce power consumption
V (internal voltage generator)
INT
reduce operating current
100
• Memory devices use several on-chip voltage generators such as an
internal Voltage generator (VINT ), a half VDD generator (VBL and
Vp ), a substrate bias generator (VBB), and a boosted voltage
generator (VPP).
• These on-chip voltages are used to reduce the operating current ,
stabilizing operations and improving performance.
Half VDD Voltage Generator
Folded bit line structure with half V DDsensing scheme
Improve noise immunity and low power consumption
Reduce electric field across thin dielectric
bias ckt driver simulated output waveforms
102
• It is composed of a bias circuit and a driver.
• The transistors in the bias circuit are sized to set the voltage of node B
to VDD/2. Therefore the voltages of node A and C are VDD/2 + Vtn
and VDD/2 -I VtpI, respectively and the output voltage of the driver is
stabilized at VDD/2.
• Since the driver transistor are weakly turned on, the static current is
very small (e.g., tens of µA).
• The push-pull driver is used to suppress any unexpected change at the
output node quickly by turning on either transistor strongly.
Negative Substrate Bias Voltage Generator(1)
Subthreshold current is major source of charge decay
Negative voltage substrate increase threshold voltage
reduce load cap. of bit
line
VT
VSB
VSB
© CMOS Digital Integrated Circuits – 4th Edition 104
SRAM
6 transistor SRAM
Advantage:
• Static Power dissipation is less.
• CMOS SRAM cell include high noise immunity.
Disadvantage:
• CMOS memories historically were larger cell size, the added
complexity of the CMOS process and the tendency to exhibit "latch-
up" phenomenon
► When the word line (RS) is not selected, i.e., when the voltage level of
Iine RS is equal to logic "O," the pass transistors M3 and M4 are turned off.
► The simple latch circuit consisting of two cross-connected inverters
preserves one of its two [Link] operating points; hence, data is being held.
► Consider the two columns, C and C bar. If all word lines in the SRAM array
are inactive, the relatively large column capacitances are charged-up by the
column pull-up transistors, MP1 and MP2.
► Select the memory cell by raising its word line voltage to logic "1," hence,
the pass transistors M3 and M4 are turned on.
► Once the memory cell is selected, four basic operations may be
performed on this cell.
Write "1" operation:
• The voltage level of column C is forced to logic-low by the data-write
circuitry. The driver transistor M1 turns off. The voltage V1, attains a
logic-high level, while V2 goes low.
Read"1" operation:
• The voltage of column C retains its precharge level while the voltage
of column C is pulled down by M2 and M4. The data-read circuitry
detects the small voltage difference (Ve> Ve) and amplifies it as a logic
"1" data output.
Write “0" operation:
• The voltage level of column C is forced to logic-low by the data-write
circuitry. The driver transistor M2 turns off. The voltage V2 attains a
logic-high level, while V1 goes low.
Read“0" operation:
• The voltage of column C retains its precharge level while the voltage
of column C is pulled down by M1 and M3. The data-read circuitry
detects the small voltage difference (Ve< Vi:) and amplifies it as a logic
"O" data output.
Read “0”
Read Operation
Write “0”
Leakage Currents in SRAM Cells
• Leakage in SRAM cells typically contributes a major portion of the standby current of the chip. Since several
millions of memory cells are integrated into the SRAM device, the leakage current of each cell is accumulated
to consume a fairly large amount of standby power.
• The leakage current of the SRAM cells consists of a junction current Ij at the data “1” node to the substrate,
subthreshold leakage current (Insub and Ipsub) flowing through turned-off nMOS and pMOS transistors and
tunnelling current (Itunneling) cross the thin gate.
• The leakage current can be reduced by increasing the threshold voltage of transistors in the cell by either
applying a negative substrate bias or using high threshold transistors.
Nonvolatile Memory
Idea: deactivation of the NMOS transistors by
raising their threshold voltage above the VOH
level through channel implants
• “1” bit stored - the corresponding transistor is
turned off through channel implant
• “0” bit stored - non-implanted (normal)
transistors Advantage: higher density (smaller
area
• A word is selected by putting to “0“ the corresponding wordline Ri.
• All the wordlines Ri are “1“ except the selected wordline which is “0”
• Each bit line consists of a depletion-load NAND gate, driven by some of the row signals, i.e.,
the word lines.
• In normal operation, all word lines are held at the logic-high voltage level except for the
selected line, which is pulled down to logic-low level.
• If a transistor exists at the crosspoint of a column and the selected row, that transistor is
turned off and the column voltage is pulled high by the load device.
• On the other hand, if no transistor exists (shorted) at that particular crosspoint, the column
voltage is pulled low by the other nMOS transistors in the multi-input NAND structure.
• Thus, a logic "1 "-bit is stored by the presence of a transistor that can be deactivated, while
a logic "0"-bit is stored by a shorted or normally on transistor at the crosspoint.
FLASH MEMORY
Ferroelectric Random Access Memory
(FRAM)
• Ferroelectric memories use a ferroelectric capacitor where the
dielectric material of the typical capacitor is replaced by a
ferroelectric material.
• Before FRAM, ferromagnetic memories using ferromagnetic cores
with hysteresis characteristics were developed in l 950s. But those
vanished due to large cell area and power consumption.
• In The hysteresis loop of a ferroelectric capacitor the total charge of the ferroelectric capacitor varies as a
function of the applied voltage. It does not disappear in the absence of the electric field<(Q, for data" l" and
-Q, for data “0").
• This is because a spontaneous polarization occurs, in the crystal, structure of the ferroelectric material. The
net change in the direction of the polarization happens when the applied electric field is larger than Vc. No
further reorientation can occur after V, and the polarization is saturated (Q, ).
• The structure and operation of FRAM are similar to those of DRAM except PL (plate line)
• Reference cells which always store only data “1' arc placed per column to generate a reference signal used
for read operation.
• Bit line, (Bl and BLB) are precharged at Vss since PPRE is high.
• A word line ( WLO) is selected and activated to a boosted voltage ( VPP) for full data restoration as in DRAM.
• A reference word line connected to the other bit line (RWLI) is activated at the same time. Step signals are
applied to normal and reference plate lines (PL and RPL.) together. The total charge of the ferroelectric
capacitor is changed to -Q, and a positive charge appears, on the bit line to maintain charge neutrality.
• When the word Iine, is enabled. capacitor divider, are formed by CF and CBL
• The capacitance of the reference cell is set to make the voltage signal
generated by the reference cell between ΔV0 and ΔV1 and is larger
than that of the normal cell.
• After voltage signals, are generated on the bit line and bit line bar by
the normal and the reference cell the bit line sense amplifier detects,
and amplifies the signal difference on bit line pair.