Integrated Circuits

A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikoli

Timing Issues
January 2003
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Timing Issues

Synchronous Timing
CLK In R1 Combinational Logic Cout R2

Cin

Out

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Timing Definitions

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Latch Parameters
D Q Clk T Clk D tc-q PWm thold td-q tsu

Delays can be different for rising and falling data transitions

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Register Parameters
D Q Clk T Clk D tsu Q tc-q Delays can be different for rising and falling data transitions
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thold

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Clock Uncertainties
4 Power Supply 3 Interconnect Devices 2 5 Temperature 1 Clock Generation 6 Capacitive Load 7 Coupling to Adjacent Lines

Sources of clock uncertainty

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Clock Nonidealities

Clock skew
Spatial variation in temporally equivalent clock edges; deterministic + random, tSK

Clock jitter
Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL

Variation of the pulse width

Important for level sensitive clocking
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Clock Skew and Jitter

Clk
tSK

Clk

tJS

Both skew and jitter affect the effective cycle time Only skew affects the race margin

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Clock Skew
# of registers Earliest occurrence Latest occurrence of Clk edge of Clk edge Nominal /2 Nominal + /2

Insertion delay Max Clk skew

Clk delay

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Positive and Negative Skew

In CLK R1 D Q tCLK1 delay (a) Positive skew R1 D Q tCLK1 delay (b) Negative skew
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Combinational Logic

R2 D Q tCLK2

Combinational Logic

R3 D Q tCLK3

delay

In

Combinational Logic

R2 D Q tCLK2

Combinational Logic

R3 D Q tCLK3

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Positive Skew
TCLK + CLK1 1

TCLK

CLK2

2
+ th

Launching edge arrives before the receiving edge

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Negative Skew
TCLK + CLK1 1 TCLK 3

CLK2

Receiving edge arrives before the launching edge

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Timing Constraints
In R1 D Q tCLK1 tc q, cd tsu, thold tc q t tlogic Combinational Logic R2 D Q tCLK2

CLK

Minimum cycle time: T - = tc-q + tsu + tlogic

Worst case is when receiving edge arrives early (positive )
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Timing Constraints
In R1 D Q tCLK1 tc q, cd tsu, thold tc q t tlogic Combinational Logic R2 D Q tCLK2

CLK

Hold time constraint: t(c-q, cd) + t(logic, cd) > thold +

Worst case is when receiving edge arrives late Race between data and clock
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Impact of Jitter

CLK

TC LK

t j itter -tji tte r

In

REGS CLK tc-q , tc-q, ts u, thold tjitter

Combinat ional Logic t log ic t log ic, cd

cd

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Longest Logic Path in Edge-Triggered Systems

TSU Clk TClk-Q TLM T TJI +

Latest point of launching

Earliest arrival of next cycle

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Clock Constraints in Edge-Triggered Systems

If launching edge is late and receiving edge is early, the data will not be too late if:

Tc-q + TLM + TSU < T TJI,1 TJI,2 -

Minimum cycle time is determined by the maximum delays through the logic

Tc-q + TLM + TSU + + 2 TJI < can Skew T be either positive or negative
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Shortest Path
Earliest point of launching

Clk

TClk-Q TLm

Clk

TH
Data must not arrive before this time

Nominal clock edge

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in Edge-Triggered Systems
If launching edge is early and receiving edge is late:

Tc-q + TLM TJI,1 < TH + TJI,2 +

Minimum logic delay

Tc-q + TLM < TH + 2TJI+

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How to counter Clock Skew?

Negative Skew REG

REG

REG In

REG

log

Out

Positive Skew Clock Distribution

Data and Clock Routing

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Flip-Flop Based Timing

Skew

Logic delay TSU

Flip-flop delay

Flip -flop

TClk-Q

Logic

= 0

= 1

Representation after M. Horowitz, VLSI Circuits 1996.

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Flip-Flops and Dynamic Logic

Logic delay TSU TSU TClk-Q TClk-Q

= 0

= 1
Logic delay

= 0

= 1

Precharge

Evaluate

Evaluate

Precharge

Flip-flops are used only with static logic

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Latch timing
tD-Q
D Clk Q

When data arrives to transparent latch Latch is a soft barrier

tClk-Q When data arrives to closed latch Data has to be re-launched

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Single-Phase Clock with Latches

Latch

Logic

Tskl Clk

Tskl

Tskt

Tskt

PW P
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Latch-Based Design
L1 latch is transparent when = 0

L2 latch is transparent when = 1

L1 Latch

Logic

L2 Latch

Logic

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Slack-borrowing
In L1 D Q a CLB_A t p d,A b L2 D Q c CLB_B t p d,B L1 d D Q e

CLK1

CLK2

TC LK

CLK1

CLK1

CLK2 slack passed to next stage t pd,A a valid tD Q tpd,B t DQ e valid d valid
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b valid c valid

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Latch-Based Timing
Static logic

Skew

L1 Latch

Logic

L2 Latch

L1 latch
Logic

= 1 = 0
Short path

L2 latch

Long path

Can tolerate skew!

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Clock Distribution

H-tree

CLK

Clock is distributed in a tree-like fashion

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More realistic H-tree

[Restle98]
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The Grid System

G D C L e r K r i v

D r iv e r

D riv e r

No rc-matching Large power

D r i v G C e r L K

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Example: DEC Alpha 21164

Clock Frequency: 300 MHz - 9.3 Million Transistors Total Clock Load: 3.75 nF Power in Clock Distribution network : 20 W (out of 50) Uses Two Level Clock Distribution: Single 6-stage driver at center of chip Secondary buffers drive left and right side clock grid in Metal3 and Metal4 Total driver size: 58 cm!

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21164 Clocking
tcycle= 3.3ns trise = 0.35ns final drivers tskew = 150ps

Clock waveform

2 phase single wire clock, distributed globally 2 distributed driver channels

Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width

pre-driver

Location of clock driver on die

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Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variation
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Clock Drivers

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Clock Skew in Alpha Processor

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EV6 (Alpha 21264) Clocking 600 MHz 0.35 micron CMOS

tcycle= 1.67ns

trise = 0.35ns Global clock waveform

tskew = 50ps 2 Phase, with multiple conditional buffered clocks

2.8 nF clock load 40 cm final driver width

PLL

Local clocks can be gated off to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking
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21264 Clocking

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EV6 Clock Results

ps 5 10 15 20 25 30 35 40 45 50 GCLK Skew
(at Vdd/2 Crossings)
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ps 300 305 310 315 320 325 330 335 340 GCLK Rise Times
(20% to 80% Extrapolated to 0% to 100%)
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EV7 Clock Hierarchy

Active Skew Management and Multiple Clock Domains
NCLK ( M e m C t r l)

+ widely dispersed drivers

DLL

+ DLLs compensate static and lowfrequency variation + divides design and verification effort

DLL

DLL

G CLK (C P U C o re )

- DLL design and verification is added work + tailored clocks

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L2L_CLK (L2 Cache)

PLL

SYSCLK

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L2R_CLK (L2 Cache)

Self-timed and Asynchronous Design

Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 1) Completion is ensured by careful timing analysis 2) Ordering of events is implicit in logic Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol
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Synchronous Pipelined Datapath

In R1 D Q tpd,reg Logic Block #1 tpd1 R2 D Q Logic Block #2 tpd2 R3 D Q tpd3 R4 D Q

CLK

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Self-Timed Pipelined Datapath

Req Ack HS Start Req Ack Done HS Start Req Ack Done HS Start Req ACK Done

In

R1

F1

R2

F2

R3

F3

Out

tpF1

tpF2

tpF3

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Completion Signal Generation

In LOGIC NETWORK Out

Start

DELAY MODULE

Done

Using Delay Element (e.g. in memories)

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Completion Signal Generation

Using Redundant Signal Encoding

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Completion Signal in DCVSL

VDD Start VDD B0 B1 B0 In1 In1 In2 In2 B1 Done

PDN

PDN

Start

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Self-Timed Adder
VDD Start C0 C0 Start VDD Start C0 C0 Start (a) Differential carry generation
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VDD C3 P3 G3 Start C4 C4 C4 C3 C2 C1 Start C3 P3 K3 C4 C4 (b) Completion signal Done C4 C3 C2 C1

P0 G0

C1

P1 G1

C2

P2 G2

P0 K0

C1

P1 K1

C2

P2 K2

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Completion Signal Using Current Sensing

Input Register VDD Static CMOS Logic GND sense Current Sensor A Done Min Delay Generator B Output A toverlap B tMDG Done Output tpd-NOR valid Start tdelay

Inputs Start

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Hand-Shaking Protocol
Req Ack SENDER Data RECEIVER Ack Req 3

(a) Sender-receiver configuration

Data

1 cycle 1

1 cycle 2 Senders action Receivers action (b) Timing diagram

Two Phase Handshake

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Event Logic The Muller-C Element

A F B (a) Schematic
VDD A B A S R (a) Logic Q F B B A B VDD B F

A 0 0 1 1

B 0 1 0 1

Fn+1 0 Fn Fn 1

(b) Truth table

VDD

(b) Majority Function (c) Dynamic

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2-Phase Handshake Protocol

Sender logic Data ready C Req Ack Handshake logic Data Receiver logic Data accepted

Advantage : FAST - minimal # of signaling events (important for global interconnect) Disadvantage : edge - sensitive, has state
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Example: Self-timed FIFO

In Out R1 En Reqi C Acki C C Acko Done Req0 R2 R3

All 1s or 0s -> pipeline empty Alternating 1s and 0s -> pipeline full

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2-Phase Protocol

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Example

From [Horowitz]
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Example

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Example

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Example

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4-Phase Handshake Protocol

2 Req 4 Senders action Receivers action Ack 3 Data 1 Cycle 1 5 1 Cycle 2

Also known as RTZ Slower, but unambiguous

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4-Phase Handshake Protocol

Implementation using Muller-C elements
Data Sender logic Data ready Req C C S Ack Receiver logic Data accepted

Handshake logic

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Self-Resetting Logic
completion detection (L1) completion detection (L2) completion detection (L3)

Precharged Logic Block (L1)

Precharged Logic Block (L2)

Precharged Logic Block (L3)

VDD

int out A B C

Post-charge logic

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Clock-Delayed Domino
GND CLK1 VDD Q1 (also D2) D1 Pulldown Network CLK2 (to next stage)

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AsynchronousSynchronous Interface

fin Asynchronous system Synchronous system fCLK Synchronization

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Synchronizers and Arbiters

Arbiter: Circuit to decide which of 2 events occurred first Synchronizer: Arbiter with clock as one of the inputs Problem: Circuit HAS to make a decision in limited time - which decision is not important Caveat: It is impossible to ensure correct operation But, we can decrease the error probability at the expense of delay

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A Simple Synchronizer
CLK int I1 Q I2

CLK

Data sampled on rising edge of the clock Latch will eventually resolve the signal value, but ... this might take infinite time!
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Synchronizer: Output Trajectories

2 .2 Vout 2 .2 22 . 2

22 2 22 2 time [ps]

22 2

Single-pole model for a flip-flop

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Mean Time to Failure

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Example
Tf = 10 nsec = T Tsignal = 50 nsec tr = 1 nsec t = 310 psec VIH - VIL = 1 V (VDD = 5 V)

N(T) = 3.9 10-9 errors/sec MTF (T) = 2.6 108 sec = 8.3 years MTF (0) = 2.5 sec
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Influence of Noise
Uniform distribution around VM p(v)

logarithmic reduction T

VIL

VIH

Initial Distribution

Still Uniform

Low amplitude noise does not influence synchronization behavior

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Typical Synchronizers
2 phase clocking circuit
Q 1 2

Using delay line

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Cascaded Synchronizers Reduce MTF

In Sync O1 Sync O2 Sync Out

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Arbiters
Req1 Req2 Arbiter Ack1 Ack2 Req2
Ack1

Req1

A B
Ack2

(a) Schematic symbol Req1 Req2 A B metastable Ack1 VT gap

(b) Implementation (c) Timing diagram t

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PLL-Based Synchronization
Chip 1 Data Digital System fsystem = N x fcrystal PLL fcrystal , 200<Mhz Crystal Oscillator Divider reference clock Digital System Chip 2

PLL Clock Buffer

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PLL Block Diagram

Reference clock Up Phase detector Down Charge pump Loop filter v VCO

Local clock

Divide by N

System Clock

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Phase Detector
ref ref Output local clock (a) VDD local clock Output

Output before filtering

Output (Low pass filtered)

(b)

Transfer characteristic
90 (c) 180 phase error (deg)

-180

-90
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Phase-Frequency Detector
Rst D Q A Rst D Q B (a) schematic A B UP DN B UP B UP = 0 DN = 1 DN UP = 0 DN = 0 UP = 1 DN = 0 A A

(b) state transition diagram A B UP DN (c) Timing waveforms

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PFD Response to Frequency

A B UP DN

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PFD Phase Transfer Characteristic

Average (UP-DN) VDD

2 2 phase error (deg)

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Charge Pump
VDD

UP DN

To VCO Control Input

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PLL Simulation
ref 1.0 0.8 0.6 0.4 ref 0.2 0.0 div 0 1 2 3 4 5 vco Time ( s) div

Control Voltage (V)

vco

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Clock Generation using DLLs

Delay-Locked Loop (Delay Line Based) fREF
U D

Phase Det

Charge Pump

DL
Filter

fO Phase-Locked Loop (VCO-Based) fREF N PD

U D

CP
Filter

VCO fO

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Delay Locked Loop

FREF PH Phase detect U D Charge C pump (a) REF OUT UP DN PH VCTRL Delay
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VCTRL VCDL FO

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DLL-Based Clock Distribution

VCDL Digital Circuit

CP/LF Phase Detector GLOBAL CLK VCDL Digital Circuit

CP/LF Phase Detector

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