Logic Design
Hisham H. Mohesan
Registers and Counters
Lecture 9
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
تصميم المحاضرة
طلبة المرحلة االولى لقسم هندسة األلكترونيك الفئة المستهدفة
ساعة 2 مدة المحاضرة
المناقشة -سؤال وجواب – العصف الذهني الطرق النشطة
المستخدمة
.عرض أنشطة ومهام للطلبة وفتح المجال للمناقشة مسار المحاضرة
.التطبيق العملي
العرض التقديمي – الورقة والقلم – الشاشة – برنامج المواد التدريبية
التعليم الكتروني -السبورة
تهيئة البيئة التعليمية االعداد اللوجستي
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
learning objective
These objectives aim to provide students with a
comprehensive understanding of registers and
counters, enabling them to design and analyze
digital circuits effectively.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Behavior objective
The student will be able to:
-Understanding the concept and purpose of registers and
counters in digital systems.
-Understanding the role of counters in counting and
sequencing tasks within digital circuits.
-Learning about different types of counters, such as
asynchronous (ripple) counters and synchronous counters.
-Gaining practical experience through hands-on activities or
simulations to design and analyze circuits involving
registers and counters.
-Understanding the applications of registers and counters in
digital systems, such as in data processing, arithmetic
operations, and control unit design.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Contents
- Basic Shift Register Operations
-Serial-in/Serial out Shift Register
-A Basic Application
-The 74HC164A Shift Register
-Waveforms for the 74HC164A
-Parallel in/Serial out Shift Register
-The 74HC165 Shift Register
-Bidirectional Shift Register
-Universal Shift Register
-Shift Register Counters
-Johnson Counter
-Home work
-Key Terms
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Basic Shift Register Operations
A shift register is an arrangement of flip-flops with
important applications in storage and movement of data.
Some basic data movements are illustrated here.
Data in
Data in Data out Data out Data in Data out
Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out
Data in
Data in
Data out Data out
Serial in/parallel out Parallel in/parallel out Rotate right Rotate left
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Serial-in/Serial out Shift Register
Shift registers are available in IC form or can be
constructed from discrete flip-flops as is shown here with a
five-bit serial-in serial-out register.
Each clock pulse will move an input bit to the next flip-
flop. For example, a 1 is shown as it moves across.
FF0 FF1 FF2 FF3 FF4
Serial 1 1 1 1 1 1 Serial
data D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 data
input output
C C C C C
CLK
CLK
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A Basic Application
An application of shift registers is conversion of serial
data to parallel form.
For example, assume the binary number 1011 is loaded
sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.
FF0
FF0 FF1
FF1 FF2
FF2 FF3
FF3
Serial
Serial 1
X
0 1
0 10
1 10 11
data
data D00
D Q00
Q D11
D Q11
Q D22
D Q22
Q D33
D Q33
Q
input
input
C
C C
C C
C C
C
CLK
CLK
CLK
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The 74HC164A Shift Register
The 74HC164A is a CMOS 8-bit serial in/parallel out shift
register. VCC can be from +2.0 V to +6.0 V.
(9)
CLR
(8)
CLK
(1)
Serial A
(2) R R R R R R R R
B
inputs C C C C C C C C
S S S S S S S S
(3) (4) (5) (6) (10) (11) (12) (13)
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
One of the two serial data inputs may be used as an active HIGH
enable to gate the other input. If no enable is needed, the other serial
input can be connected to VCC. The 74HC164A has an active LOW
asynchronous clear. Data is entered on the leading-edge of the clock.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Waveforms for the 74HC164A
Sample waveforms for CLR
the 74HC164A are Serial
A
shown. Notice that B B
inputs
acts as an active HIGH CLK
enable for the data on Q0
A as discussed. Q1
As with CMOS Q2
devices, unused inputs Q3
should always be Outputs
Q
connected to a logic
4
Q
level; unused outputs 5
Q
should be left open. 6
Q7
Clear Clear
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Parallel in/Serial out Shift Register
Shift registers can be used to convert parallel data to serial
form. A logic diagram for this type of register is shown:
D0 D1 D2 D3
SHIFT/LOAD
G1 G5 G2 G6 G3 G7 G4
Serial
D D D D
Q0 Q1 Q2 Q3 data out
C C C C
FF0 FF1 FF2 FF3
CLK
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The 74HC165 Shift Register
The 74HC165 is a CMOS 8-bit parallel in/serial out shift
register. The logic symbol is shown:
D0 D1 D2 D3 D4 D5 D6 D7
(11) (12) (13) (14) (3) (4) (5) (6)
(1) (9)
SH/LD (10) SRG 8 Q7
SER
(15)
CLK INH (2) (7)
CLK C Q7
The clock (CLK) and clock inhibit (CLK INH) lines are connected to a
common OR gate, so either of these inputs can be used as an active-
LOW clock enable with the other as the clock input. Data is loaded
asynchronously when SH/LD is LOW and moved through the register
synchronously when SH/LD is HIGH and a rising clock pulse occurs.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The 74HC165 Shift Register
A Multisim simulation of the 74165A is shown. The word generator is
used as a source for the pattern shown in the green probes.
MSB
Q7 is labeled QH
in Multisim
Pattern is loaded
when J1 is LOW
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The 74HC165 Shift Register
Here the scope is opened and you can observe the pattern. The MSB is
HIGH and is on the Q7 output as soon as LOAD is LOW.
MSB
Q7
Load
Clk
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Bidirectional Shift Register
Bidirectional shift registers can shift the data in either
direction using a RIGHT/LEFT input.
The logic analyzer simulation shows a bidirectional shift register
such as the one shown in Figure 9-19 of the text. Notice the HIGH
level from the Serial data in is shifted at first from Q3 toward Q0.
CLK
RIGHT/LEFT Shift left Shift right
Serial data in
Q0
Q1
Q2
Q3
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Bidirectional Shift Register
How will the pattern change if the RIGHT/LEFT control
signal is inverted?
See display
CLK
RIGHT/LEFT Shift
Shiftleft
right Shift Shift
right left
Serial data in
Q0
Q1
Q2
Q3
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Universal Shift Register
A universal shift register has both serial and parallel
input and output capability. The 74HC194 is an example
of a 4-bit bidirectional universal shift register.
D0 D1 D2 D3
(3) (4) (5) (6)
(1)
CLR SRG 4
(9)
S0
(10)
S1
(2)
SR SER
(7)
SL SER
(11)
CLK C
(15) (14) (13) (12)
Q0 Q1 Q2 Q3
Sample waveforms are
on the following slide…
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Universal Shift Register
CLK
Mode S0
control
inputs S1
CLR
Serial SR SER
data
inputs SL SER
D0
Parallel D1
data
inputs D2
D3
Q0
Q1
Parallel
outputs
Q2
Q3
Shift right Shift left Inhibit
Clear Load Clear
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Shift Register Counters
Shift registers can form useful counters by recirculating
a pattern of 0’s and 1’s. Two important shift register
counters are the Johnson counter and the ring counter.
FF0 FF1 FF2 FF3
The Johnson counter can D0 Q0 D1 Q1 D2 Q2 D3 Q3
be made with a series of D C C C C
flip-flops Q3 Q3
CLK
… or with a series of J-K J0
FF0
Q0 J1
FF1
Q1 J2
FF2
Q2 J3
FF3
Q3
Q3
flip flops. Here Q3 and Q3
C C C C
are fed back to the J and K K0 Q0 K1 Q1 K2 Q2 K3 Q3
Q3
inputs with a “twist”.
CLK
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Johnson Counter
Redrawing the same Johnson counter (without the clock
shown) illustrates why it is sometimes called as a “twisted-
ring” counter.
FF0
J0 Q0
“twist” C
K0 Q0
Q3
Q3
Q3
Q3
K1
J1
C
FF3
FF1
C
Q1
Q1
J3
K3
2 Q 2 K
2 Q 2 J
2 FF
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Johnson Counter
The Johnson counter is useful when you need a sequence
that changes by only one bit at a time but it has a limited
number of states (2n, where n = number of stages).
The first five counts for a 4-bit Johnson counter that is
initially cleared are: CLK Q0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
What are the remaining 3 states? 7 0 0 0 1
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Home work
A 4-bit parallel-in/parallel-out shift
register will store data for
a. 1 clock period
b. 2 clock periods
c. 3 clock periods
d. 4 clock periods
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Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Home work
A possible sequence for a 4-bit ring counter is
a. … 1111, 1110, 1101 …
b. … 0000, 0001, 0010 …
c. … 0001, 0011, 0111 …
d. … 1000, 0100, 0010 …
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Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Home work
For transmission, data from a UART is sent in
a. asynchronous serial form
b. synchronous parallel form
c. can be either of the above
d. none of the above
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Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Key Terms
Register One or more flip-flops used to store and shift data.
Stage One storage element in a register.
Shift To move binary data from stage to stage within a
shift register or other storage device or to move
binary data into or out of the device.
Load To enter data in a shift register.
Bidirectional Having two directions. In a bidirectional shift
register, the stored data can be shifted right or left.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
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Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved