Department of Collegiate and Technical Education
Department of
Electronics & Communication Engineering
HDL LABORATORY (18ECL58)
( V Semester)
Experiment No -2
Full Adder
Session # 1
Department of Electronics and Communication Engineering – 18ECL58
Experiment No – 1.
AIM: Model in Verilog for a full adder and add functionality to
perform logical operations of XOR, XNOR, AND & OR gates. Write
test bench with appropriate input patterns to verify the modelled
behaviour
OBJECTIVES:
1. Write a Verilog Code for Full Adder using Structural Model.
2. For these circuits observe and record waveforms.
3. Synthesize and download the code on a FPGA board.
Department of Electronics and Communication Engineering – 18ECL58
THEORY :
Full Adder is a combinational circuit that forms the arithmetic
sum ,the adder which adds three inputs and produces two outputs.
The first two inputs are A and B and the third input is an input carry
as C-IN carry from the previous lower significant position.. The
output carry is designated as C-OUT and the normal output is
designated as S which is SUM.
A Full adder can also be implemented with two half adder and one
OR Gate
Department of Electronics and Communication Engineering – 18ECL58
Block Diagram:
Department of Electronics and Communication Engineering – 18ECL58
Circuit diagram
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Logical expressions:
Half sum, s = a ⊕ b
sum = s⊕cin
cout= a*b + s*cin
Conditions to Verify AND, OR, XOR and XNOR:
Condition 1:Whencin = 0,
sum = s⊕ 0 =s =a ⊕ b = XOR gate
cout= a*b + s*0 = a*b = a&b = AND gate
Condition 2:Whencin =1,
sum = s⊕ 1 = s’ 1 + 1’ s = s’ = a’b’ + ab = XNOR gate
cout= a*b + s*1 = ab + ab’ + a’b = a (b+b’) + a’b = a+a’b =(a+a’) (a+b) =a+b = OR gate
Department of Electronics and Communication Engineering – 18ECL58
Truth Table :
Inputs Output
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Department of Electronics and Communication Engineering – 18ECL58
Truth Table to Verify AND, OR, XOR and XNOR Gates:
Inputs Outputs
a b a and b a or b a xor b axnor b
0 0 0 0 0 1
0 1 0 1 1 0
1 0 0 1 1 0
1 1 1 1 0 1
Department of Electronics and Communication Engineering – 18ECL58
Verilog Code
// i) Full adder code: //Full adder Test bench:
module fulladder (a,b,cin,sum,cout); module basicGate_FA_tb_v;
input a,b,cin; reg a,b;
output sum, cout; Wire aandb,aorb,axorb,axnorb;
wire s; basicGate_FAuut(.a(a), .b(b), .aandb(aand
assign s = a^b; b), .aorb(aorb), .axorb(axorb), .axnorb(axn
assign sum = s^cin; orb));
assign cout = (a&b) | (s&cin); initial
endmodule begin
// ii) Basic Gates Code a = 0; b = 0; #10
modulebasicGate_FA(a,b,aandb, aorb, a = 0; b = 1; #10
axorb, axnorb); a = 1; b = 0; #10
input a,b; a = 1; b = 1; #10;
output aandb, aorb, axorb, axnorb; end
fulladder f1(a,b,1'b0, axorb,aandb); endmodule
fulladder f2(a,b,1'b1, axnorb,aorb);
endmodule
Department of Electronics and Communication Engineering – 18ECL58
Waveform/ Timing Diagram
RESULT: The waveforms are for full adder is observed and
verified.
Department of Electronics and Communication Engineering – 18ECL58
LMS-KARNATAKA
E-CONTENT MODERATOR: Dr. Revanna C R
Assistant Professor
Department of Electronics & Communication
Government Engineering College, Ramanagara
E-CONTENT DEVELOPER: 1. Dr. HARISH H M
Assistant Professor
Department of Electronics & Communication
Government Engineering College, Haveri
2. NOOR FATHIMA
Assistant Professor
Department of Electronics & Communication
Government Engineering College, Ramanagara
Department of Electronics and Communication Engineering – 18ECL58
THANK YOU
Department of Electronics and Communication Engineering – 18ECL58