Chapter 4

HW Specification of 8086
System Configuration
Interfacing
4.1. Introduction
This unit explains how to design and implement an 8086 based microcomputer
system.
 how 8086 microprocessor is interfaced with memory and peripherals
 how an 8086 based microcomputer system works

Main Topics:
 Pins and Signals
 Mode of operations
 Components
 Bus Structure and Operations
 Clock generation
 Latching and Buffering
 System Configuration
 System Design and Interfacing
4.2. The 8086 Microprocessor
The 8086, announced in 1978, was the first 16-bit microprocessor
introduced by Intel.
It is characterized by:
 Time-multiplexed address and data bus:
• has a 16-bit data bus, &
• a 20-bit address bus
 ability to address up to 1Mbyte of memory
 can address up to 64K of byte-wide input/output ports
 Two mode of operations:
• Minimum Mode
• Maximum Mode
 manufactured using high-performance metal-oxide semiconductor (HMOS) technology
 approximately 29,000 transistors
 housed in a 40-pin dual in-line package.
4.3. 8086-Based System
Components :An 8086-based microcomputer system has the following
components
 Microprocessors:
4.4. Pin Diagram and Signals
The 8086 MP is housed in a 40-pin
dual in-line package.
This package can be mounted into a
socket that is soldered to the circuit
board, or its leads inserted through
holes in the board and soldered.
Different
control/data/address/power/clock
signals are pinned out to each lead
A number of the pins serve dual
functions
4.4. Pin Diagram and Signals (Cont.)
Depending on the mode of operation selected, the assignments for a
number of the pins on the microprocessor package are changed.
Accordingly, the signals of the 8086 microprocessor can be grouped
into three categories:
1. Signals having common function to both modes of operation
2. Signals having special function for minimum mode
3. Signals having special function for minimum mode
4.4. Pin Diagram and Signals (Cont.)
4.5. Electrical Characteristics
the power supply ratings of these processors and their input and
output electrical characteristics
that power is applied between pin 40 (Vcc) and pins 1(GND) and
20(GND).
Pins 1 and 20 should be connected together.
The nominal value of Vcc is specified as +5V DC with a tolerance of
+/-10%.
 i.e, 8086 will operate correctly as long as the difference in voltage between Vcc and GND
is greater than 4.5 V dc and less than 5.5 V dc.
At room temperature (25°C), both the 8088 and 8086 draw a
maximum of 340 mA from the supply.
4.5. Electrical Characteristics
the power supply ratings of these processors and their input and
output electrical characteristics
Input Characteristics of 8086/88

 Output Characteristics of 8086/88

4.6. System Clock
To establish the bus cycle time, the CPU requires an external clock
signal.
The time base for synchronization of the internal and external
operations of the microprocessor in a microcomputer system is
provided by the clock (CLK) input signal.
 At pin number 19
 the 8086 is available in three different speeds
As an integral part of the 8086 family, Intel offers the 8284 Clock
Generator/Driver for this purpose.
the 8284 Clock Generator:
 provide the primary (system) clock signal, and
 the hardware reset interface and the mechanism for the insertion of wait states in the
bus cycle. i.e, READY/RESET-control
4.6. System Clock (Cont.)

Figure: Clock Circuit and Interfacing of 8284 clock generator with 8086/88
4.7. 8086 System Bus Structure & Operation
The 8086 has a common address and data bus.
 It is commonly known as time multiplexed address and data bus.
 i.e. address and data appear on common bus at different time intervals.
 This multiplexed address and data bus has to be de-multiplexed externally
with the use of latches and the ALE signal
4.7. Cont
If no bus cycles are required, the microprocessor performs what are
known as idle states. During these states, no bus activity takes place.
Each idle state is one clock period long, and any number of them can
be inserted between bus cycles. Idle states are performed if the
instruction queue inside the microprocessor is full and it does not
need to read or write operands from memory
Wait states can also be inserted into a bus cycle. This is done in
response to a request by an event in external hardware instead of an
internal event such as a full queue. In fact, the READY input of the
MPU is provided specifically for this purpose.
4.7. (Cont.)
the BIU's bus cycle:
To explain the operation of the time multiplexed bus, the BIU's bus cycle must
be examined.
Essentially, a bus cycle is an asynchronous event in which the address' of an
1I0 peripheral or memory location is presented, followed by either a read
control signal (to capture or "read" the data from the addressed device) or a
write control signal and the associated data (to transmit or "write" the data to
the addressed device). The selected. device (memory or 1I0 ; peripheral)
accepts the data on the bus during a write cycle or places the requested data
on the bus during a read cycle. On termination of the' cycle, the device
latches the data written or removes the'data read.
4.7. Cont.
4.8. System Configurations
A unique feature of the 8086 and 8088 CPUs is the ability of a user to
define a subset of the CPU's control signal outputs in order to tailor
the CPU to its intended system environment.
There are two mode of operations:
Minimum Mode, &
Maximum Mode
4.8. (Cont.)- Minimum Mode
1. In Minimum Mode:
The MN/MX pin strapped to +5V
the CPU supports small, single-processor systems
consist of a few devices and that use the system bus
the CPU itself generates all bus control signals (DT/R, DEN, ALE
and. either M/IO or IO/M) and the command output signal (RD,
WR or INTA), and provides a mechanism for requesting bus access
(HOLD/HLDA)
4.8. (Cont.)- Minimum Mode Signals & Pins
4.8. (Cont.)- Minimum Mode Configuration
4.8. (Cont.) – Maximum Mode
2. In Maximum Mode:
The MN/MX pin strapped to ground
the CPU supports multi-processor systems
The system is consisting of two or more processors
Bus Controller(8288) is added to provide a sophisticated bus
control function and compatibility with the Multi-bus architecture
Intel® 8289 Bus Arbiter is used with the 8288 which permits the
CPU to support multiple processors on the system bus
The bus controller, rather than the CPU, provides all bus control
and command outputs
4.8. (Cont.)- Maximum Mode Signals/Pins
4.8. (Cont.) – Maximum Mode Configuration
4.9. Interfacing
Interfacing is a process of joining different equipment to a
microprocessor so that a specific task shall be worked out.