Module II Shrink Down
Approaches
OUTLINE
The MOSFET (cont’d)
• Velocity saturation
• Short channel effect
• MOSFET scaling approach
MOSFET Scaling
• MOSFETs have been steadily miniaturized over time
– 1970s: ~ 10 m
– Today: ~30 nm
• Reasons:
– Improved circuit operating speed
– Increased device density --> lower cost per function
Benefit of Transistor Scaling
As MOSFET lateral dimensions (e.g. channel length L) are reduced:
• IDsat increases decreased effective “R”
• gate and junction areas decrease decreased load “C”
faster charging/discharging (i.e. d is decreased)
Velocity Saturation
Velocity saturation limits IDsat in sub-micron MOSFETS
v for < sat
Simple model:
1
sat
v vsat for sat
Esat is the electric field at velocity saturation: sat
2vsat
8 106 cm/s for electrons in Si
vsat
6 10 6
cm/s for holes in Si
MOSFET I-V with Velocity Saturation
In the linear region:
W m
Coxe eff VGS VT VDS VDS
L 2
ID
VDS
1
sat L
long channel I D
ID
VDS
1
sat L
Drain Saturation Voltage, VDsat
• If satL >> VGS-VT then the MOSFET is considered
“long-channel”. This condition can be satisfied when
– L is large, or
– VGS is close to VT
1
VDsat
m
1
VGS VT sat L
sat
2vsat
Example: Drain Saturation Voltage
Question: For VGS = 1.8 V, find VDsat for an NMOSFET with
Toxe = 3 nm, VT = 0.25 V, and WT = 45 nm, if L =
(a) 10 m, (b) 1 m, (c) 0.1 m (d) 0.05 m
Solution: From VGS , VT and Toxe, eff is 200 cm2V-1s-1.
Esat= 2vsat / eff = 8 104 V/cm
m = 1 + 3Toxe/WT = 1.2
1
m 1
VDsat
VGS VT sat L
1
m 1
VDsat
VGS VT sat L
(a) L = 10 m: VDsat= (1/1.3V + 1/80V)-1 = 1.3 V
(b) L = 1 m: VDsat= (1/1.3V + 1/8V)-1 = 1.1 V
(c) L = 0.1 m: VDsat= (1/1.3V + 1/.8V)-1 = 0.5 V
(d) L = 0.05 m: VDsat= (1/1.3V + 1/.4V)-1 = 0.3 V
IDsat with Velocity Saturation
Substituting VDsat for VDS in the linear-region ID equation gives
W
Coxe eff VGS VT
2
2 mL long channel I Dsat
I Dsat
VGS VT VGS VT
1 1
m sat L m sat L
For very short channel length: sat L VGS VT / m
sat Coxe eff VGS VT Wvsat Coxe VGS VT
W
I Dsat
2
• IDsat is proportional to VGS–VT rather than (VGS – VT)2
• IDsat is not dependent on L
gs
Short- vs. Long-Channel NMOSFET
0.0
0 1 2 2.5
V (V) ds
0.4 0.03
(a) (b)
L = 0.15 m L = 2.0 m Vgs = 2.5V
V gs = 2.5V
Vt = 0.4 V Vt = 0.7 V
0.3
I ds (mA/m)
0.02
V gs = 2.0V
Ids (A/m)
Vgs = 2.0V
0.2
V gs = 1.5V
0.01
Vgs = 1.5V
0.1 V gs = 1.0V
Vgs = 1.0V
0.0 0.0
0 1 2 2.5
V ds (V) Vds (V)
(b)
Short-channel
0.03 NMOSFET:
• IDsatL =is2.0proportional
m to VGS-VTn rather than (VGS-VTn)2
Vgs = 2.5V
V = 0.7 V
• VDsatt is lower than for long-channel MOSFET
0.02
• Channel-length modulation is apparent
/m)
Vgs = 2.0V
Velocity Overshoot
• When L is comparable to or less than the mean free
path, some of the electrons travel through the channel
without experiencing a single scattering event
projectile-like motion (“ballistic transport”)
The average velocity of carriers exceeds vsat
e.g. 35% for L = 0.12 m NMOSFET
Effectively, vsat and sat increase when L is very small
The Short Channel Effect (SCE)
“VT roll-off”
• |VT| decreases with L
– Effect is exacerbated by
high values of |VDS|
• This effect is undesirable (i.e. we want to minimize it!)
because circuit designers would like VT to be invariant
with transistor dimensions and bias condition
Qualitative Explanation of SCE
• Before an inversion layer forms beneath the gate, the
surface of the Si underneath the gate must be
depleted (to a depth WT)
• The source & drain pn junctions assist in depleting the
Si underneath the gate
– Portions of the depletion charge in the channel region are
balanced by charge in S/D regions, rather than by charge on
the gate
Less gate charge is required to invert the semiconductor
surface (i.e. |VT| decreases)
The smaller L is, the greater the percentage of
depletion charge balanced by the S/D pn junctions:
depletion
charge
supported VG
by gate
(simplified rj
n+ n+
analysis)
p depletion region
Large L: Small L:
S D S D
Depletion charge Depletion charge
supported by S/D supported by S/D
First-Order Analysis of SCE
• The gate supports the depletion charge in the trapezoidal region.
This is smaller than the rectangular depletion region underneath
the gate, by the factor
L L
1 WT
2L
• This is the factor by which the depletion charge Qdep is reduced
from the ideal
• One can deduce from simple geometric analysis that
2WT
L L 2 r j 1 1
rj
VT Roll-Off: First-Order Model
qN AWT rj 2WT
VT VT ( long channel) VT 1 1
Coxe L rj
Minimize VT by
• reducing Toxe
• reducing rj
• increasing NA
(trade-offs: degraded eff, m)
MOSFET vertical dimensions should be
scaled along with horizontal dimensions!
MOSFET Scaling: Constant-Field Approach
• MOSFET dimensions and the operating voltage (VDD) each are
scaled by the same factor >1, so that the electric field
remains unchanged.
Constant-Field Scaling Benefits
• Circuit speed
improves by
• Power dissipation
per function
is reduced by 2
• Since VT cannot be scaled down aggressively, the operating
voltage (VDD) has not been scaled down in proportion to the
MOSFET channel length:
MOSFET Scaling: Generalized Approach
• Electric field intensity increases by a factor >1
• Nbody must be scaled up by to suppress short-channel effects
• Reliability and
power density
are issues