Creating and Adding Custom IP
Zynq
Vivado 2015.2 Version
This material exempt per Department of Commerce license exception TSU © Copyright 2015 Xilinx
Objectives
After completing this module, you will be able to:
– List various AXI interfaces
– Describe the AXI4 transactions
– Summarize the AXI4 valid/ready acknowledgment model
– List the steps involved in creating and packaging IP
Creating Custom IP 21- 2 © Copyright 2015 Xilinx
Outline
AXI Interfaces
AXI4 Transactions
IP Packager
Custom IP
Summary
Creating Custom IP 21- 3 © Copyright 2015 Xilinx
AXI is Part of ARM’s AMBA
AMBA
AMBA 3.0
APB AHB AXI (2003)
Older Performance Newer
AMBA: Advanced Microcontroller Bus Architecture
AXI: Advanced Extensible Interface
Creating Custom IP 21- 4 © Copyright 2015 Xilinx
AXI is Part of AMBA
AMBA
Enhancements for FPGAs
APB AHB AXI ATB AMBA 3.0
(2003)
Same Spec
AXI-4 AXI-4 AXI-4 AMBA 4.0
(2010)
Memory Map Stream Lite
Interface Features Similar to
Memory Map / Full Traditional Address/Data Burst PLBv46, PCI
(AXI4) (single address, multiple data)
Streaming Data-Only, Burst Local Link / DSP Interfaces / FIFO /
(AXI4-Stream) FSL
Lite Traditional Address/Data—No Burst PLBv46-single
(AXI4-Lite) (single address, single data) OPB
Creating Custom IP 21- 5 © Copyright 2015 Xilinx
Basic AXI Signaling – 5 Channels
1. Read Address Channel
2. Read Data Channel
3. Write Address Channel
4. Write Data Channel
5. Write Response Channel
Creating Custom IP 21- 6 © Copyright 2015 Xilinx
The AXI Interface—AXI4-Lite
No burst
Data width 32 or 64 only AXI4-Lite Read
– Xilinx IP only supports 32-bits
Very small footprint
Bridging to AXI4 handled
automatically by AXI4-Lite Write
AXI_Interconnect (if needed)
Creating Custom IP 21- 7 © Copyright 2015 Xilinx
The AXI Interface—AXI4
Sometimes called “Full AXI” or “AXI
Memory Mapped”
AXI4 Read
– Not ARM-sanctioned names
Single address multiple data
– Burst up to 256 data beats
Data Width parameterizable
– 1024 bits AXI4 Write
Creating Custom IP 21- 8 © Copyright 2015 Xilinx
The AXI Interface—AXI4-Stream
No address channel, no read and write,
always just master to slave AXI4-Stream Transfer
– Effectively an AXI4 “write data” channel
Unlimited burst length
– AXI4 max 256
– AXI4-Lite does not burst
Virtually same signaling as AXI Data
Channels
– Protocol allows merging, packing, width
conversion
– Supports sparse, continuous, aligned,
unaligned streams
Creating Custom IP 21- 9 © Copyright 2015 Xilinx
Outline
AXI Interfaces
AXI4 Transactions
IP Packager
Custom IP
Summary
Creating Custom IP 21- 10 © Copyright 2015 Xilinx
All AXI Channels Use A Basic “VALID/READY” Handshake
SOURCE asserts and holds VALID when DATA is available
DESTINATION asserts READY if able to accept DATA
DATA transferred when VALID and READY = 1
SOURCE sends next DATA (if an actual data channel) or de-asserts VALID
DESTINATION deasserts READY if no longer able to accept DATA
Creating Custom IP 21- 11 © Copyright 2015 Xilinx
AXI Interface: Handshaking
AXI uses a valid/ready handshake
acknowledge
Each channel has its own valid/ready
– Address (read/write) Inserting Wait States
– Data (read/write)
– Response (write only)
Flexible signaling functionality
– Inserting wait states
Always Ready
– Always ready
– Same cycle acknowledge
Same Cycle Acknowledge
Creating Custom IP 21- 12 © Copyright 2015 Xilinx
AXI Interconnect
axi_interconnect component
– Highly configurable
• Pass Through
• Conversion Only
• N-to-1 Interconnect
N=16
• 1-to-N Interconnect
• N-to-M Interconnect – full crossbar
• N-to-M Interconnect – shared bus structure
Decoupled master and slave interfaces
Xilinx AXI Reference Guide(UG761)
Creating Custom IP 21- 13 © Copyright 2015 Xilinx
AXI4 Signals (AXI4, AXI4-Lite)
Creating Custom IP 21- 14 © Copyright 2015 Xilinx
Outline
AXI Interfaces
AXI4 Transactions
IP Packager
Custom IP
Summary
Creating Custom IP 21- 15 © Copyright 2015 Xilinx
Reusing Your IP
IP from many sources can be packaged and made available in Vivado
All IP available in the Vivado IP Catalog can be used to create IP Integrator designs
Any IP Integrator diagram can be quickly packaged as a single complex IP
Standardized IP-XACT
representation Vivado IP Integrator
Source (C, RTL, IP, etc) IP Catalog
Simulation Models
Xilinx IP
Documentation IP Packager
Example Designs 3rd Party IP
Test Bench
User IP
Creating Custom IP 21- 16 © Copyright 2015 Xilinx
IP-XACT
Industry Standard (IEEE) XML format to describe IP using meta-data
– Ports
– Interfaces
– Configurable Parameters
– Files, documentation
IP-XACT only describes high level information about IP, not low level
description, so does not replace HDL or Software.
Enables automatic connection, configuration and integration
Enables integration of 3rd Party IP
– (And Export of your own IP)
Creating Custom IP 21- 17 © Copyright 2015 Xilinx
IP Packager
The IP Packager allows a core to be
packaged and included in the IP
Catalog, or for distribution
– IP-XACT
– Complete set of files include
• Source code, Constraints, Test Benches
(simulation files), documentation
IP Packager can be run from Vivado
– On the current project
– On a specified directory
– New AXI IP
IP Packager can be accessed through
Manage IP link flow
Creating Custom IP 21- 18 © Copyright 2015 Xilinx
IP Packager Configuration
Modify configuration
– Properties
– Compatibility
– Files
– Custom parameters
– Ports and Interfaces
– Address and Memory
– GUI customization
Select Add, Edit or
Options change defaults
Creating Custom IP 21- 19 © Copyright 2015 Xilinx
IP Repository
Uses [Link] file of the IP
Specify the directory in the repository
Displays IP in the repository
Creating Custom IP 21- 20 © Copyright 2015 Xilinx
Outline
AXI Interfaces
AXI4 Transactions
IP Packager
Custom IP
Summary
Creating Custom IP 21- 21 © Copyright 2015 Xilinx
Create Custom IP
Generates HDL template for
– Slave/Master
• AXI Lite/Full/Stream
Generates
– Software Driver
– Test Software Application
– AXI4 BFM Example
– AXI4 Debug Hardware Simulation demonstration
design
Next Steps
– Add IP in the repository
– Edit IP
• Typically you will select this to add the functionality
Creating Custom IP 21- 22 © Copyright 2015 Xilinx
Generated Template for AXI Lite
HDL implementation of AXI Interface
– 32 bit data width
User specifies required number of
registers (minimum 4)
Read/write to/from Registers
implemented
User logic can be easily connected
User logic can be a hierarchical design
Creating Custom IP 21- 23 © Copyright 2015 Xilinx
HDL AXI Lite
Connect user logic to registers, or modify design
Address
Register
Data
Creating Custom IP 21- 24 © Copyright 2015 Xilinx
Generated Template for AXI Full
HDL AXI Full Interface
– 32 bit data interface
Burst transaction support
implemented
– Specify size of memory space
– Up to 1024 Bytes
Example code implementing block
memory
– User logic can connect or replace this
section
Creating Custom IP 21- 25 © Copyright 2015 Xilinx
Files created
[Link] src
– IP XACT description – Imported source files
bd Examples design
– Block Diagram tcl file xgui
drivers – GUI tcl file
– SDK and software files
• Simple register read/write functionality
hdl
– Verilog/VHDL source
Creating Custom IP 21- 26 © Copyright 2015 Xilinx
Using the IP
Modify template, add user logic
– Add hdl files used by the added user logic
Package IP
Specify IP directory in the Vivado repository
– Project settings
Use in IP Catalog like any other IP
Creating Custom IP 21- 27 © Copyright 2015 Xilinx
Outline
AXI Interfaces
AXI4 Transactions
IP Packager
Custom IP
Summary
Creating Custom IP 21- 28 © Copyright 2015 Xilinx
Summary
AXI4 interface defines five channels
– All channels use basic VALID/READY handshake to complete a transfer
AXI Interconnect extends AXI interface by allowing 1-to-N, N-to-1, N-to-M, and M-to-N
connections
Create and Import wizard supports AXI Lite, Full, and Stream compatible IP creation
– Handles interface side protocol
– Provides template to add HDL functionality
Custom IP can be imported using IP Packager
Include in the IP Repository for reuse across projects
Creating Custom IP 21- 29 © Copyright 2015 Xilinx