8259
Programmable Interrupt Controller
(SUB: Microprocessor and Interfaces)
PREPARED BY:
ER. MOHIT MISHRA
ASSOCIATE PROFESSOR
COMPUTER SCIENCE DEPARTMENT
TOPIC COVERED
• BASICS AND FEATURES OF 8259
• PIN DIAGRAM AND DESCRIPTION
• BLOCK DIAGRAM AND ITS DESCRIPTION
BASICS AND FEATURES OF 8259
● The 8259 programmable interrupt controller (PIC)
adds eight vectored priority encoded interrupts to the
microprocessor.
● It accepts request from the peripheral equipment,
determine which of the incoming requests is of the
highest importance
● Special features of 8259:
● Eight level priority controller
● Expandable to 64 levels
● Programmable interrupt modes
● Individual request mash capability
It is packaged in a 28-pin DIP, uses NMOS technology and requires a single a5V supply.
Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and real time overhead in handling
multi-level priority interrupts.
It has several modes, permitting optimization for a variety of system requirements
INTERRUPT REQUEST REGISTER (IRR) AND
IN-SERVICE REGISTER (ISR)
The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt
Request Register (IRR) and the In-Service (ISR). The IRR is used to store all the interrupt levels
which are requesting service; and the ISR is used to store all the interrupt levels which are being
serviced.
PRIORITY RESOLVER
This logic block determines the priorities of the bits set in the IRR. The highest priority is
selected and stroed into the corresponding bit of the ISR during INTA pulse.
INTERRUPT MASK REGISTER (IMR
The IMR stores the bits which mask the interrupt lines to be masked. The IMR operates on
the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower
quality.
INT (INTERRUPT)
This output goes directly to the CPU interrupt input. The V level on this line is designed to
be fully compatible with the 8080A, 8085A and 8086 input
levels.
INTA (INTERRUPT ACKNOWLEDGE)
INTA pulses will cause the 8259A to release vectoring information onto the data bus. The format of this
data depends on the system mode (mPM) of the 8259A.
DATA BUS BUFFER
This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system Data Bus. Control
words and status information are transferred through the Data Bus Buffer.
READ/WRITE CONTROL LOGIC
The function of this block is to accept Output commands from the CPU. It contains the Initialization
Command Word (ICW) registers and Operation Command Word (OCW) registers which store the various
control formats for device operation. This function block also allows the status of the 8259A to be
transferred onto the Data Bus.
CS (CHIP SELECT)
A LOW on this input enables the 8259A. No reading or writing of the chip will occur unless the device
is selected.
WR (WRITE)
A LOW on this input enables the CPU to write control words (ICWs and OCWs) to the 8259A.
RD (READ)
A LOW on this input enables the 8259A to send the status of the Interrupt Request Register (IRR), In
Service Register (ISR), the Interrupt Mask Register (IMR), or the Interrupt level onto the Data Bus.
A0
This input signal is used in conjunction with WR and RD signals to write commands into the various
command registers, as well as reading the various status registers of the chip. This line can be tied directly to
one of the address lines
.