Unit IV:

Programmable Logic Devices

By
Dr. Anup Vibhute
Dr. D Y Patil Institute of Technology, Pimpri, Pune
Contents:
• Syllabus
• Classification of Devices
• PAL
• PLA
• CPLD and FPGA
• Memory devices
Syllabus:
• Programmable logic devices: Detail architecture, Study of PROM, PAL, PLA,
General Architecture, features and typical specifications of FPGA and CPLD.
• Semiconductor memories: memory organization and operation, expanding
memory size, Classification and characteristics of memories, RAM ROM,
EPROM, EEPROM, NVRAM, SRAM, and DRAM. Designing combinational
circuits using PLDs

Course Outcome:
• CO6:Design combinational digital systems using PLD.
• CO6.1: Design Combinational circuits using PAL, PLA
• CO6.2: Differentiate between the different types of memories
Introduction:
• A programmable logic device is an IC that is user configurable and is capable of
implementing logic functions.
• A PLD contains a large number of gates, flip-flops, and registers that are
interconnected on the chip.
• Many of the connections, however, are fusible links that can be broken.
• The IC is said to be programmable because the specific function of the IC for a
given application is determined by the selective breaking of some of the
interconnections while leaving others intact.
• The ‘fuse blowing’ process can be done either by the manufacturer in
accordance with the customer’s instructions, or by the customer himself.
• This process is called ‘programming’ because it produces the desired circuit
pattern interconnecting the gates, flip-flops, registers, and so on.
• PLDs can be reprogrammed in a few seconds and hence give more
flexibility to experiment with designs
Introduction:
• Advantages of PLDs over fixed function ICs are as follows:
• Low development cost
• Less space requirement
• Less power requirement
• High reliability
• Easy circuit testing
• Easy design modification
• High design security
• Less design time
• High switching speed
• PLDs have many of the advantages of ASICs as given below:
• Higher densities
• Lower quantity production costs
• Design security
• Reduced power requirement
• Reduced space requirement
Introduction:
• Programmable logic devices can be divided into three distinct architectural
groups.
• Simple Programmable Logic Devices – SPLDs
• Complex Programmable Logic Devices – CPLDs
• Field Programmable Gate Arrays – FPGAs
SPLD:
• SPLDs are the simplest, smallest and least-expensive type of programmable logic
device.
• The term SPLD covers several types of device:
• Read Only Memory (ROM)
• Programmable Logic Array (PLA) – This device has both programmable AND
and OR planes.
• Field Programmable Logic Array (FPLA) – Same as PLA but can be erased and
reprogrammed
• Programmable Array Logic (PAL) – This device has a programmable AND plane
and a fixed OR plane
• Generic Array Logic (GAL) – This device has the same logical properties as the
PAL but can be erased and reprogrammed
• 
SPLD:
• A general structure of an SPLD 
SPLD:
• ROM, PAL and PLA are the three varieties that are quite similar to each other.
• They all have an input connection matrix, which connects the inputs of the device
to an array of AND-gate.
• They all have an output connection matrix, which connect the outputs of the
AND-gates to the inputs of OR-gates which drive the outputs of the device.
• The given logic SOP function can be implemented using AND and OR arrays.
Programming Techniques:
• Fusible link technology-
Programming Techniques:
• Anti-fuse Technology:
•  In antifuse technologies , the un-programmed device has links which are very
high in resistance.
Programming Techniques:
PLD Notations:
PLD Notations:
ROM as PLD:
• A ROM which can be programmed is called a PROM.
• The process of entering information in a ROM is known as programming.
• ROMs are used to store information which is of fixed type
• The advantages of using a ROM as a PLD are the following:
• Ease of design since no simplification or minimization of logic function is required.
• Designs can be changed, modified rapidly.
• It is usually faster than discrete MSI/SSI circuit.
• Cost is reduced.

• Disadvantages :
• Non-utilization of complete circuit
• Increased power requirement
• Enormous increase in size with increase in the number of input variables making it impractical
ROM as PLD:
ROM as PLD:
• Design a combinational circuit using a ROM. The circuit accepts a 3-bit number
and generates an output binary number equal to the square of the input number.
ROM as PLD:
• Design a combinational circuit using a ROM. The circuit accepts a 3-bit number
and generates an output binary number equal to the square of the input number.
ROM as PLD:
• Give the logic implementation of a 8 × 4 bit ROM using a decoder of a suitable size
• An 8 × 4 bit ROM is to be implemented. It consists of eight words of four bits each. 8 words can
be addressed by 3 bits. Hence 3 to 8 decoder can be used to implement the logic.
Programmable Array Logic (PAL):
• A PAL (programmable array logic) consists of a programmable array of AND
gates that connects to a fixed array of OR gates.
• PALs are implemented with fuse process technology and are, therefore, one-time
programmable (OTP).
• Because only the AND gates are programmable, the PAL is easier to program but
is not as flexible as the PLA.
• The PAL structure allows any sum-of-products (SOP) logic expression with a
defined number of variables to be implemented
Programmable Array Logic (PAL):
• It is a 3-input 3-wide AND-OR structure.
Programmable Array Logic (PAL):
• Implement the following Boolean functions using PAL with four inputs
and 3-wide AND-OR structure. Also write the PAL programming table.
F1(A, B, C, D) = ∑ m(2, 12, 13)
F2(A, B, C, D) = ∑ m(7, 8, 9, 10, 11, 12, 13, 14, 15)
F3(A, B, C, D) = ∑ m(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
F4(A, B, C, D) = ∑ m(1, 2, 8, 12, 13).

• Write K-map first and reduce the Boolean equation for given function
• Write PAL programming table
• Draw the circuit diagram
Programmable Array Logic (PAL):
• Write K-map first and reduce the Boolean equation for given function
Programmable Array Logic (PAL):
• Write PAL programming table
Programmable Array Logic (PAL):
• Draw the circuit diagram
Programmable Logic Array (PLA):
• The PLA represents another type of programmable logic which combines the
characteristics of the PROM and the PAL
• It provides both a programmable OR array and a programmable AND array, i.e. in
a PLA both AND gates and OR gates have fuses at the inputs
• A third set of fuses in the output inverters allows the output function to be inverted
if required. Usually X-OR gates are used for controlled inversion. This feature
makes it the most versatile of the three PLDs.
• PLA can be mask programmable or field programmable
• Mask programmable- programmed by manufacturer
• Field programmable- programmed by user
Programmable Logic Array (PLA):
• The general structure will be as follows
• Steps-
• Truth table and K- Map
• Reduce equation
• Implement Circuit
Programmable Logic Array (PLA):
• Full Adder using PLA
Programmable Logic Array (PLA):
• Full Adder using PLA
Programmable Logic Array (PLA):
• PLA Programming Table:
Programmable Logic Array (PLA):
• Implement the following two Boolean functions with a PLA:
• F1(A, B, C) = ∑ m(0, 1, 2, 4)
• F2(A, B, C) = ∑ m(0, 5, 6, 7)

Product term Inputs Output

A B C F1 F2
1 0 - 0 1 -
2 - 0 0 1 -
3 0 0 - 1 -
4 0 0 0 - 1
5 AB 1 1 - - 1
6 AC 1 - 1 - 1
Programmable Logic Array (PLA):
Difference between PROM, PAL and PLA
 Complex Programmable Logic Devices (CPLD):
• PLA, PAL, PROM, GAL have a limited number of inputs, product terms and
outputs. These devices support only 32 I/O numbers.
• Multiple SPLD have disadvantages as follows:
1. PCB size increases with number of chips
2. Connecting wires will result in adverse capacitive effect
3. Power requirement increases with number of chips
4. Cost increases

• The complex programmable logic device (CPLD) is basically a single device

containing multiple SPLDs and providing more capacity for larger logic designs.
• A CPLD (complex programmable logic device) consists basically of multiple
SPLD arrays with programmable interconnections.
Complex Programmable Logic Devices (CPLD):
CPLD: Xilinx 9500 CPLD:
• The XC9500 CPLD family provides advanced in-system programming and test
capabilities for high performance, general purpose logic integration
• All devices are in-system programmable for a minimum of 10,000 program/erase
cycles.
• An expanded JTAG instruction set allows version control of programming
patterns and in-system debugging
• I/Os may be configured for 3.3V or 5V operation. All outputs provide 24 mA
drive
• Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs)
and I/O Blocks (IOBs) fully interconnected by the Fast CONNECT™ switch
matrix.
CPLD: Xilinx 9500 CPLD:
CPLD: Xilinx 9500 CPLD:
• Function Block:
• Each FB provides programmable logic capability with 36 inputs and 18 outputs.
• Each Function Block is comprised of 18 independent macrocells, each capable of
implementing a combinatorial or registered function. T
• The FB also receives global clock, output enable, and set/reset signals.
CPLD: Xilinx 9500 CPLD:
• Macrocell:
• The macrocell register can be configured as a D-type or T-type flip-flop, or it may be
bypassed for combinatorial operation.
CPLD: Xilinx 9500 CPLD:
• Product Term Allocator
• The product term allocator controls how the five direct product terms are assigned
to each macrocell.
• The product term allocator can re-assign other product terms within the FB to
increase the logic capacity of a microcell beyond five direct terms.
• Up to 15 product terms can be available to a single macrocell
CPLD: Xilinx 9500 CPLD:
• In system Programming:
• XC9500 devices are programmed in-system via a standard 4-pin JTAG protocol
(IEEE 1149.1 boundary-scan (JTAG)
CPLD: Xilinx 9500 CPLD: Xilinx 9500 Features:
 Flexible 36V18 Function Block
• Xilinx 9500 Features:
- 90 product terms drive any or all of 18
• High-performance macrocells within Function Block
• - 5 ns pin-to-pin logic delays on all pins - Global and product term clocks, output
enables, set and reset signals
• - fCNT to 125 MHz
- Extensive IEEE Std 1149.1 boundary-scan
• Large density range (JTAG) support
• - 36 to 288 macrocells with 800 to 6,400 - Programmable power reduction mode in each
usable gates macrocell
- Slew rate control on individual outputs
• 5V in-system programmable
- User programmable ground pin capability
• - Endurance of 10,000 program/erase
- Extended pattern security features for design
cycles
protection
• - Program/erase over full commercial - High-drive 24 mA outputs
voltage and temperature range
- 3.3V or 5V I/O capability
• Enhanced pin-locking architecture -Advanced CMOS 5V FastFLASH™ technology
•  - Supports parallel programming of multiple
XC9500 devices
CPLD: Xilinx 9500 CPLD:
• Applications:
• Random glue logic in prototyping small gate arrays, implementing critical control
designs such as graphics controllers, cache control, UARTs, LAN controllers and
many more.
• particularly attractive in portable applications such as mobile phones, digital
assistants and so on.
Field Programmable Gate Array (FPGA):
• It is not practical to increase the logic capacity with a CPLD architecture beyond a
certain point.
• The FPGA (field-programmable gate array) differs in architecture, does not use
PAL/PLA type arrays, and has much greater densities than CPLDs
• The logic-producing elements in FPGAs are generally much smaller than in
CPLDs, and there are many more of them.
• Also, the programmable interconnections are generally organized in a row and
column arrangement in FPGAs.
• The first FPGA was introduced by Xilinx
• It has arrays of logic blocks which are programmable. It is surrounded by
PROGRAMMABLE ROUTING RESOURCES, which allows the user to define
the interconnections between the logic blocks.
• It also has lots of very flexible input and output circuits (programmable for TTL,
CMOS and other interface standards).
Field Programmable Gate Array (FPGA):
Field Programmable Gate Array (FPGA):
• Configurable Logic Blocks:
• Typically, an FPGA logic block consists of several smaller logic modules that are
the basic building units, Somewhat analogous to macrocells in a CPLD
• fundamental configurable logic blocks (CLBs) within the global row/column
programmable interconnects that are used to connect logic blocks
Field Programmable Gate Array (FPGA):
• Logic Module:
• A logic module consists of LUT (Look Up Table), a D Flipflop and a Multiplexer.
Most of the FPGAs are having 4 input LUT. Output of the LUT may become
direct output of Logic module or input to D FF.
Field Programmable Gate Array (FPGA):
• LUT-
• A LUT consists of programmable memory and it can be used to generate logic function in
SOP form.
• A memory can generate canonical product form.
• A LUT consists a memory and a MUX.
• The limit on the size of the truth table is N, where N represents the number of inputs to
the LUT.
• For the general N-input LUT, the number of memory locations accessed by the table is 2N.
Field Programmable Gate Array (FPGA):
• Programmable I/O
• The programmable I/O pads are used to interface the logic blocks and routing
architecture to the external components.
• The I/O pad and the surrounding logic circuit form as an I/O cell.
•  Programming Technologies
• There are a number of programming technologies that have been used for
reconfigurable architectures.
• Some of the well known technologies include static memory (SRAM), flash and
anti-fuse.
Field Programmable Gate Array (FPGA):
• Applications:
• Specific application of an FPGA includes
• digital signal processing,
• bioinformatics,
• device controllers,
• software-defined radio,
• random logic,
• ASIC prototyping,
• medical imaging,
• computer hardware emulation,
• integrating multiple SPLDs, 
• voice recognition,
• cryptography,
• filtering and communication encoding and many more
Difference between CPLD and FPGA
Parameter CPLD FPGA
Cost It is less expensive It is more expensive
Power Consumption Low High
Flexibility Less More
Security High Low
Basic Building Blocks PLD CLB
Functionality PAL-And OR logic LUT
implementation
Complexity Less More
Density of gates 10000 to 1 milllion Upto 10000
Speed High High
Delays Predictable Non predictable
Programability Reprogrammed for limited Reprogrammed for as
times possible as
Application Simple applications Complex applications