EMBEDDED SYSTEM
Analog to Digital Conversion
ATMEGA32 ADC Features:
10-bit
8 input channels
Converted data his held in tow special registers ADCL and ADCH
ADCH:ADCL is 16 bits; ADC data 10-bits; 6 bits are unused
Option of making either upper 6 bits or lower 6 bits unused
Three options for Vref; VrefAVCC, Vrefinternal 2.56V, Vrefexternal
AREF pin
Analog to Digital Conversion
Connection for ADC: Following connection provide stable VCC and Vref
ADC Registers
Five major registers associated
ADCH (High data)
ADCL (Low data)
ADCSRA (ADC control and status register)
ADMUX (ADC multiplexer selection register)
SPIOR (Special function I/O register)
ADMUX Registers
REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0
REFS1:0 Bit 7:8 Reference selection bits
Reference voltage for ADC
REFS1 REFS0 Vref
0 0 AREF pin Set externally
0 1 AVCC pin Same as VCC
1 0 Reserved -------
1 1 Internal 2.56 V Fixed regardless of VCC value
ADMUX Registers
REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0
ADLAR Bit 5 ADC left adjust result
ADLAR = 1Left adjusted ; ADLAR = 0 Right Adjusted ; ADCH:ADCL
ADCH ADCL
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X ADLAR = 1
X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ADLAR = 0
ADMUX Registers
REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0
MUX4:0 Bit 4:0 Analog channel and Gain selection bits
Gain for diff. channel; Combination of analog I/P connected to ADC
MUX 4…0 Single ended Input MUX 4…0 Single ended Input
00000 ADC0 00100 ADC4
00001 ADC1 00101 ADC5
00010 ADC2 00110 ADC6
00011 ADC3 00111 ADC7
ADCSRA Registers
ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0
ADEN Bit 7 ADC enable
ADEN = 1 Enable ADC; ADEN = 0 Disable ADC
ADSC Bit 6 ADC Start conversion
ADSC = 1 Start conversion; ADSC = 0 Stop conversion
ADATE Bit 5 ADC Auto trigger enable
ADATE = 1 Auto trigger
ADCSRA Registers
ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0
ADIF Bit 4 ADC interrupt flag
ADC sets ADIF = 1 when conversion is completed
ADIE Bit 3 ADC interrupt enable
Setting ADIE = 1 enables the ADC conversion complete interrupt
ADSP2:0 Bit 2:0 ADC pre-scaler select bits
Determine the division factor b/w XTAL frequency and input clock to ADC
ADCSRA Registers
ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0
ADSP2:0 Bit 2:0 ADC pre-scaler select bits
Determine the division factor b/w XTAL frequency and input clock to ADC
Programming A/D Converter
Two methods of using ADC
Polling method
Interrupt method
Steps for polling method
1. Make pin for selected ADC channel as input pin
2. Turn on the ADC module because it is disabled by default
3. Select conversion speed; ADPS2:0
Programming A/D Converter
4. Select voltage reference and ADC input channel
Voltage reference : REFS0 and REFS1 bit in ADMUX
ADC input channel: MUX4:0 bits in ADMUX
5. Activate Start conversion ADSC = 1 of ADCSRA
6. Wait for conversion to complete by polling ADIF bit of ADCSRA
7. When ADIF = 1 Read ADCL and ADCH
Read ADCL before ADCH otherwise result will not be valid
Programming A/D Converter
/*-------------------------------------------------------------------------------------------------------------
*Frequency of Operation = 8Mhz -->> 125ns one instruction
*while ADC takes 25 ADC cycle in first conversion and after that it will take 13 ADC clock cycle
*ADC prescaller is 128-->> 8MHz/128 = 62.5KHz
*1 ADC clock cycle = 16 us
*1 conversion takes minimum 400us
*---------------------------------------------------------------------------------------------------------------*/
.INCLUDE "[Link]« ;ADD Atmega32 definition
.ORG 00;Origin at 0x00
;--------------------------------------------------------------------------------------------------------
LDI R16, 0x00 ; define portA input
OUT DDRA, R16
LDI R16, 0xFF ;define portb OUTput for DAC
OUT DDRB, R16
LDI R16, 0x87
OUT ADCSRA, R16 ; enable ADC, ADC clock = ck/128
LDI R16, 0xE1
OUT ADMUX, R16 ; ADC1, Left adjustment result, Vref = 2.56V and ADC1 select
READ_ADC: NOP
SBI ADCSRA, ADSC ; Start ADC Conversion
KEEP_POLLING: NOP ; Wait the end of conversion
SBIS ADCSRA, ADIF ; Is it end of conversion yet?
RJMP KEEP_POLLING ; Keep polling until END of conversion
SBI ADCSRA, ADIF ; write 1 to clear ADIF flag
IN R20, ADCL ;ADCL register should be read first
IN R21, ADCH ;Read ADCH after ADCL
;------------------------------------------------------------------------------------------------------------
OUT PORTB, R21 ;Put result at DAC input port which is connected to PORTB IN this case
;The whole result is in R21(Most significant Byte) and R20(Least significant Byte)
;--------------------------------------------------------------------------------------------------------------
RJMP READ_ADC ; Go for Next input sample