Figure 7 1
Micro programmed Control Organization.
External Input
Control word
Next address Generator (Sequencer)
Control address register
Control memory (Rom)
Control data register
Next-address information
Chapter # 7
Figure 7 2
Selection of Address for control memory.
Instruction code
Mapping logic Statu s bits
Branch Logic
MUX Select
Multiplexers Subroutine registers (SBR) Control address register Incrementer
Control memory Select a status bit
Branch address
Micro operations
Chapter # 7
Figure 7 3
Mapping from instruction code to micro instruction address.
Opcode Computer instruction
1 0 1 1
Address
00
Mapping bits
0 x x x
x
Microinstruction address
0 0
Chapter # 7
Figure 7 4
Computer hardware configuration.
MUX
10 0
AR
10 0 Address
PC
Memory 2048 x 16
MUX
6 0 6 0 15 0
SBR
CAR
DR Arithmetic logic and shift unit
15 0
Control memory 128 x 20
Control unit
AC
Chapter # 7
Figure 7 5
Computer instructions.
15
14
11 10
Opcode
Address
(a) Instruction format
Symbol ADD BRANCH STORE EXCHANGE 0000
Code 0001 0010 0011
Description Ac Ac + M [EA] if (AC < 0) then (PC EA) M [EA] AC AC M [EA], M [EA] AC
EA is the effective address
(b) Four computer instructions
Chapter # 7
Figure 7 5
Micro instructions code format.
F1
F2
F3
CD
BR
AD
F1, F2, F3: Micro operation fields CD: Condition for branching BR: Branch field AD: Address field
Chapter # 7
Table 7-1
Symbol and Binary Code for Micro instructions
F1 000 001 010 011 100 101 110 111 F2 000 001 010 011 100 101 110 Micro operation None AC AC + DR AC 0 AC AC + 1 AC DR AR DR (0-10) AR PC M [AR] DR Micro operation None AC AC DR AC AC DR AC AC ^ DR DR M [AR] DR AC DR DR + 1 Symbol NOP ADD CLRAC INCAC DRTAC DRTAR PCTAR WRITE Symbol NOP SUB OR AND READ ACTDR INCDR
Continued Chapter # 7
Table 7-1
Symbol and Binary Code for Micro instructions
F3 000 001 010 011 100 101 110 111 CD Condition 00 Always = 1 Unconditional branch 01 DR (15) 10 AC (15) 11 AC = 0 Micro operation None AC AC DR AC AC AC shl AC AC shl AC PC PC + 1 PC AR Reserved Symbol NOP XOR COM SHL SHR INCPC ARTPC
Symbol I S Z
Comments U Indirect address bit Sign bit of AC Zero value in AC
Continued Chapter # 7
Table 7-1
Symbol and Binary Code for Micro instructions
BR
00 01 condition = 1 10 11 0
Symbol
JMP CALL RET MAP
CAR AD if condition = 1 CAR CAR + 1 if condition = 0 CAR AD, SBR CAR + 1 if CAR CAR + 1 if condition = 0 CAR SBR (Return from subroutine) CAR (2-5) DR (11-14), CAR (1, 1, 6)
Function
Chapter # 7
Fetch Routine
AR PC DR M [AR], PC PC + 1 AR DR (0-10), CAR (2-5) DR (11-14), 0 CAR (0, 1, 6)
Assembly language convention of fetch
ORG 64
FETCH:
PCTAR READ,INCPC DRTAR
U U U
JMP JMP MAP
NEXT NEXT
Bit representation of the program
Binary Address 1000000 1000001 1000010 F1 110 000 101 F2 000 100 000 F3 000 101 000 CD 00 00 00 00 00 11 BR AD 1000001 1000010 0000000
Chapter # 7
Table 7-2
Symbol Micro program.
Label AD
ADD:
Micro operations
ORG 0 NOP READ ADD ORG 4 NOP NOP NOP ARTPC ORG 8 NOP ACTDR WRITE ORG 12 NOP READ ACTDR, DRTAC WRITE
CD
BR
I U U S U I U I U U I U U U
CALL JMP JMP JMP JMP CALL JMP CALL JMP JMP CALL JMP JMP JMP
INDRCT NEXT FETCH OVER FETCH INDRCT FETCH INDRCT NEXT FETCH INDRCT NEXT NEXT FETCH
BRANCH: OVER:
STORE:
EXCHANGE:
Chapter # 7
Continued
Table 7-2
Symbol Micro program.
Label Micro operations FETCH: INDRCT: CD U U U U U BR JMP UMP MAP JMP RET AD NEXT NEXT NEXT
ORG 64 PCTAR READ, INCPC DRTAR READ DRTAR
Chapter # 7
Table 7-3
Binary Micro program for control memory.
Address
.Routine AD ADD 0 1 2 3 BRANCH 0000110 5 6 7 STORE 8 9 10 11 EXCHANGE 12 13 14 FETCH 64 15 1000001 65 1000010 66 0000000 INDRCT 1000100 67 68 1000010 1000011 1000100 101 000 101 000 000 100 000 000 000 00 00 00 11 00 10 Decimal 0000000 0000001 0000010 0000011 4 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 1000000 0001111 1000001 Binary 000 000 001 000 0000100 000 000 000 000 000 111 000 000 001 100 110 111 000 000 100 000 000 000 000 000 000 101 000 000 000 000 101 000 000
Binary Micro instructions
F1 000 000 000 000 000 000 000 110 000 000 000 000 000 000 000 000 000 F2 01 00 00 00 000 00 01 00 01 00 00 00 01 00 00 00 00 00 F3 01 00 00 00 000 00 01 00 01 00 00 00 01 00 00 00 00 00 CD 1000011 0000010 1000000 1000000 10 1000000 1000011 1000000 1000011 0001010 1000000 1000000 1000011 0001110 0001111 1000000 BR
00
100 101
Chapter # 7
0000000
Figure 7-7
Decoding of Micro instruction field.
F1 F2 F3
3 x 8 decoder
7 6 5 4 3 2 1 0
3 x 8 decoder
7 6 5 4 3 2 1 0 AN D
3 x 8 decoder
7 6 5 4 3 2 1 0
DRTA C
AD D
Arithmetic logic shift unit
PCTAR
DRTAR
From PC
From DR (0-10)
LOAD Select 0 1 Multiplexers
11 LOA D
AC
AR
CLOCK
Chapter # 7
Figure 7-8
Micro program sequencer for control memory.
External (Map)
I0 I1 T
Input Logic
Test
3 0 S1 So
LOA D
MUX 1
SBR
I I S Z
MUX 2
Select
CAR
Incremente r
Control Memory
Microop s CD BR AD
Chapter # 7
Table 7-4
Input Logic Truth table for Micro program Sequencer
0 BR Field 0 0 0 0 0 0 1 1 0 11 0 0 0L 1 1 0 1 0 Input
1
0 0 1 1 0
0 MUX 1 S1 1 0 1 x
0 0 SBR Load
O
0 0 0 1 1 x
0 1 0 0 0 1 1 0 1 1
Chapter # 7