GENERIC OFF LINE BIST ARCHITECTURE

[Link] Srinivas

Sekhar 1250210108

DIGITAL SYSTEMS TESTING & TESTABLE DESIGN

18/7/2011

INTRODUCTION

We consider BIST approaches for testing a single block of combinational logic

Here we will consider general off-line BIST structures that are applicable to chips and boards consisting of blocks of combinational logic interconnected by storage cells
2

DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN

18/7/2011

Off line BIST architecture consists of several key elements namely

Test pattern generators (TPG) Output response analyzers (ORA) The circuit under test (CUT) The distribution system (DIST) The BIST controller
18/7/2011

Digital systems testing and testable design

Generic form of Centralized and separate BIST architecture

DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN

18/7/2011

Off-line BIST architecture at the chip level and board level can be classified according to the following criteria

Centralized or Distributed BIST circuitry

Embedded or Separate BIST elements

Generic form of distributed and separate BIST architectures Here each cut is associated with its own TPG and ORA circuitary These leads to more overhead but less test time Accurate diagnosis
DIGITAL SYSTEM TESTING AND TESTABLE DESIGN

18/7/2011

Generic form of distributed and Embedded BIST architecture

Here TPG and ORA elements are configured from functional elements with in the CUT, such as registers Advantage : This leads to more complex design to control and
DIGITAL SYSTEM TESTING AND TESTABLE DESIGN

has less hard ware 18/7/2011

The choice of BIST architecture is a function of several factors , some of which are listed below .
       

Degree of test parallelism Fault coverage Levels of packaging Test time Physical constraints Complexity of replaceable units Factory and field test and repair strategy Performance degradation
8

DIGITAL SYSTEM TESTING AND TESTABLE DESIGN

18/7/2011

Specific BIST architectures

Several BIST architectures proposed by various research and development groups

Centralized and Sepreate Board level BIST architecture (CSBL) Built in Evaluation and Self Test architecture (BEST)
9

DIGITALSYSTEM TESTING AND TESTABLE DESIGN

18/7/2011

Centralized and Separate Board level BIST architecture (CSBL)

Centralized and Separate BIST architecture No boundary scan Combinational or Sequential CUT

10
DIGITALSYSTEM TESTING AND TESTABLE DESIGN

18/7/2011

A centralized and separate BIST architecture (CSBL)

11

Built in Evaluation and Self Test architecture (BEST)

The built in evaluation and self test architecture is an application of the CSBL design to chips

The below figure shows BEST architecture

12

DIGITAL SYSEM TESTING AND TESTABLE DESING

18/7/2011

In General logic being tested is a sequential circuit The inputs to the CUT are driven my a PRPG and the outputs are compressed using a MISR Either a MUX can be used or PIs can be loaded into the PRPG and then loaded into the CUT . The same concept applied to the output Both Embedded and Separate version of architecture exists
13

DIGITAL SYSTEM TESTING AND TESTABLE DESIGN

18/7/2011

Embedded : PIs and POs to the CUT go directly to registers and driven by registers

Separated : PRPG and MISR need to be added to the CUT

Here the BIST architecture results in low fault coverage because they are based on the testing sequential circuits
14

DIGITALs SYSTEM TESTING AND TESTABLE DESIGN

18/7/2011

CONCLUSION

To over come this problem an internal scan path can be used with in the CUT

So that the testing of CUT can be reduced to the problem of testing the combinational logic.

15

DIGITAL SYSTEM TESTING AND TESTABLE DESGN

18/7/2011

THANK YOU

16

DIGITAL SYSETM TESTING AND TESTABLE DESIGN

18/7/2011