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Chapter 4

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Sunil Kumar
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0% found this document useful (0 votes)
5 views34 pages

Chapter 4

Uploaded by

Sunil Kumar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd

Integrated Circuits

A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

The Wire
July 30, 2002
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The Wire

transmitters

receivers

schematics
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physical
Wires
2

Interconnect Impact on Chip

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Wire Models

All-inclusive model

Capacitance-only

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Impact of Interconnect Parasitics


Interconnect

parasitics

reduce reliability affect performance and power consumption


Classes

of parasitics

Capacitive Resistive Inductive


5

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Nature of Interconnect
Local Interconnect
Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II

No of nets (Log Scale)

SLocal = STechnology

Global Interconnect SGlobal = SDie

10

100

1,000 Length (u)

10,000

100,000

Source: Intel

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INTERCONNECT

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Capacitance of Wire Interconnect


VDD M2 Vin Cgd12 Cdb2 Vout Cdb1 Cw Cg4 VDD

M4 Vout2

M1

Cg3

M3

Interconnect

Fanout

Simplified Model

Vin

Vout
CL

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Capacitance: The Parallel Plate Model


Current flow L W Electrical-field lines

H tdi Dielectric Substrate

di cint = WL t di
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S Cwire =

S 1 = S SL SL

Wires

Permittivity

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Fringing Capacitance

(a)
H W - H/2

(b)
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Fringing versus Parallel Plate

(from [Bakoglu89])
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Interwire Capacitance

fringing

parallel

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Impact of Interwire Capacitance

(from [Bakoglu89])
14

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Wiring Capacitances (0.25 m CMOS)

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INTERCONNECT

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Wire Resistance
R= L HW
L H

Sheet Resistance Ro R1 R2

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Interconnect Resistance

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Dealing with Resistance


Selective

Technology Scaling Use Better Interconnect Materials


reduce average wire-length e.g. copper, silicides
More

Interconnect Layers

reduce average wire-length

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Polycide Gate MOSFET


Silicide PolySilicon SiO2

n+ p

n+

Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly

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Sheet Resistance

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Modern Interconnect

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Example: Intel 0.25 micron Process


5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric

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INTERCONNECT

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Interconnect Modeling

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The Lumped Model


Vout cwi re Driver

R d r iv e r

Vo u t

V in C lu m
p e d

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The Lumped RC-Model The Elmore Delay

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The Ellmore Delay RC Chain

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Wire Model
Assume: Wire modeled by N equal-length segments

For large values of N:

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The Distributed RC-line

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Step-response of RC wire as a function of time and space


2.5 x= L/10 2 x = L/4 1.5 voltage (V) x = L/2 1 x= L 0.5

0 0 0.5 1 1.5 2 2.5 time (nsec) 3 3.5 4 4.5 5

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RCModels

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Driving an RC-line
Rs

(r w,cw,L)

Vo u t

Vi n

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Design Rules of Thumb

rc delays should only be considered when tpRC >> tpgate of the driving gate

Lcrit >> tpgate/0.38rc

rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line

trise < RC
when not met, the change in the signal is slower than the propagation delay of the wire
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MJIrwin, PSU, 2000

Wires

34

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