The ARM Architecture
T TM
1L
Agenda
UNIT-1
TOPIC:1. 2. 3. 4. 5.
ARM PROCESSOR FUNDAMENTALS ARM VERSIONS ARM INSTRUCTIONS SET ARM PROGRAMMING MODEL ARM ASSEMBLY LANGUAGE
39v10 The ARM Architecture
TM
1. ARM PROCESSOR FUNDAMENTALS:ARM is short for Advanced Risc Machines Ltd. Founded 1990, owned by Acorn & Apple Known before becoming ARM as computer manufacturer Acorn which developed a 32-bit RISC processor for it s own use . The ARM is a 32-bit architecture. When used in relation to the ARM: Byte means 8 bits Half word means 16 bits (two bytes) Word means 32 bits (four bytes) Most ARM s implement two instruction sets 32-bit ARM Instruction Set 16-bit Thumb Instruction Set Jazelle cores can also execute Java byte code
39v10 The ARM Architecture
TM
Why ARM here?
ARM is one of the most licensed and thus widespread processor cores in the world
Used especially in portable devices due to low power consumption and reasonable performance (MIPS / watt)
Several interesting extensions available or in development like Thumb instruction set and Jazelle Java machine
39v10 The ARM Architecture
TM
2. ARM VERSIONS:-
Processor cores: ARM6, ARM7, ARM9, ARM10, ARM11 Extensions: Thumb, El Segundo, Jazelle etc. IP-blocks: UART, GPIO, memory controllers, etc
39v10 The ARM Architecture
TM
ARM architecture
39v10 The ARM Architecture
TM
Processor Modes
The ARM has seven basic operating modes:
User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised IRQ : entered when a low priority (normal) interrupt is raised Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode
39v10 The ARM Architecture
TM
[Link] PROGRAMING MODEL (The ARM Register Set)
Current Visible Registers
Abort Undef Mode SVC Mode IRQ Mode FIQ Mode User
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr
Banked out Registers
User
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)
FIQ
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)
IRQ
SVC
Undef
Abort
r13 (sp) r14 (lr)
r13 (sp) r14 (lr)
r13 (sp) r14 (lr)
r13 (sp) r14 (lr)
spsr
spsr
spsr
spsr
spsr
39v10 The ARM Architecture
TM
Register Organization Summary
User
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr spsr spsr spsr spsr
FIQ
IRQ
SVC
Undef
Abort
User mode r0-r7, r15, and cpsr
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)
User mode r0-r12, r15, and cpsr
User mode r0-r12, r15, and cpsr
User mode r0-r12, r15, and cpsr
User mode r0-r12, r15, and cpsr
Thumb state Low registers
Thumb state High registers
r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr)
Note: System mode uses the User mode register set
39v10 The ARM Architecture
TM
The Registers
ARM has 37 registers all of which are 32-bits long.
1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers
The current processor mode governs which of several banks is accessible. Each mode can access
a particular set of r0-r12 registers a particular r13 (the stack pointer, sp) and r14 (the link register, lr) the program counter, r15 (pc) the current program status register, cpsr
Privileged modes (except System) can also access
a particular spsr (saved program status register)
39v10 The ARM Architecture
TM
10
10
Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0
N Z C V Q f
n s
e x
I F T c
mode
Condition code flags
Interrupt Disable bits.
N = Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out V = ALU operation oVerflowed
I = 1: Disables the IRQ. F = 1: Disables the FIQ.
T Bit
Sticky Overflow flag - Q flag
Architecture 5TE/J only Indicates if saturation has occurred
Architecture xT only T = 0: Processor in ARM state T = 1: Processor in Thumb state
Mode bits
J bit
Specify the processor mode
Architecture 5TEJ only J = 1: Processor in Jazelle state
39v10 The ARM Architecture
TM
11
11
Program Counter (r15)
When the processor is executing in ARM state:
All instructions are 32 bits wide All instructions must be word aligned Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned).
When the processor is executing in Thumb state:
All instructions are 16 bits wide All instructions must be halfword aligned Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned).
When the processor is executing in Jazelle state:
All instructions are 8 bits wide Processor performs a word access to read 4 instructions at once
39v10 The ARM Architecture
TM
12
12
Development of the ARM Architecture
Halfword and signed halfword / byte support System mode
4
SA-110 SA-1110
1 2 3
Early ARM architectures
Improved ARM/Thumb Interworking CLZ
5TE
Jazelle Java bytecode execution ARM9EJ-S ARM7EJ-S
5TEJ
Saturated maths DSP multiplyaccumulate instructions ARM1020E
ARM926EJ-S ARM1026EJ-S
Thumb instruction set ARM7TDMI ARM720T
SIMD Instructions Multi-processing V6 Memory architecture (VMSA) Unaligned data support
4T
ARM9TDMI ARM940T
XScale ARM9E-S ARM966E-S
ARM1136EJ-S
39v10 The ARM Architecture
TM
13
13
Conditional Execution and Flags
ARM instructions can be made to execute conditionally by postfixing them with the appropriate condition code field.
This improves code density and performance by reducing the number of forward branch instructions.
CMP BEQ ADD skip r3,#0 skip r0,r1,r2 CMP r3,#0 ADDNE r0,r1,r2
By default, data processing instructions do not affect the condition code flags but the flags can be optionally set by using S. CMP does not need S.
loop SUBS r1,r1,#1 BNE loop
decrement r1 and set flags if Z flag clear then branch
39v10 The ARM Architecture
TM
14
14
Condition Codes
The possible condition codes are listed below:
Note AL is the default and does not need to be specified
Suffix Description Equal Not equal Unsigned higher or same Unsigned lower Minus Positive or Zero Overflow No overflow Unsigned higher Unsigned lower or same Greater or equal Less than Greater than Less than or equal Always Flags tested Z=1 Z=0 C=1 C=0 N=1 N=0 V=1 V=0 C=1 & Z=0 C=0 or Z=1 N=V N!=V Z=0 & N=V Z=1 or N=!V
EQ NE CS/HS CC/LO MI PL VS VC HI LS GE LT GT LE AL
39v10 The ARM Architecture
TM
15
15
INSTRUCTIONS SETS
Branch instructions:Branch : B{<cond>} label Branch with Link : BL{<cond>} sub_routine_label
Link bit 0 = Branch
1 = Branch with link
The offset for branch instructions is calculated by the assembler: By taking the difference between the branch instruction and the
target address minus 8 (to allow for the pipeline).
This gives a 26 bit offset which is right shifted 2 bits (as the
bottom two bits are always zero as instructions are word aligned) and stored into the instruction encoding.
This gives a range of 32 Mbytes.
TM
39v10 The ARM Architecture
16
16
Branch instructions
Branch : Branch with Link :
B{<cond>} label BL{<cond>} subroutine_label
31
28 27
25 24 23
Cond
1 0 1 L
Offset
Link bit
0 = Branch 1 = Branch with link
Condition field
The processor core shifts the offset field left by 2 positions, sign-extends it and adds it to the PC
32 Mbyte range How to perform longer branches?
17
39v10 The ARM Architecture
TM
17
Data processing Instructions
Consist of :
Arithmetic: Logical: Comparisons: Data movement:
ADD AND CMP MOV
ADC ORR CMN MVN
SUB EOR TST
SBC BIC TEQ
RSB
RSC
These instructions only work on registers, NOT memory. Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2
Comparisons set flags only - they do not specify Rd Data movement does not specify Rn
Second operand is sent to the ALU via barrel shifter.
39v10 The ARM Architecture
TM
18
18
The Barrel Shifter
LSL : Logical Left Shift
CF
ASR: Arithmetic Right Shift
0
Destination
Destination
CF
Multiplication by a power of 2
Division by a power of 2, preserving the sign bit
LSR : Logical Shift Right
...0
ROR: Rotate Right
Destination
CF
Destination
Division by a power of 2
CF
Bit rotate with wrap around from LSB to MSB
RRX: Rotate Right Extended
Destination
CF
Single bit rotate with wrap around from CF to MSB
39v10 The ARM Architecture
TM
19
19
Using the Barrel Shifter: The Second Operand
Operand 1 Operand 2
Register, optionally with shift operation
Shift value can be either be:
5 bit unsigned integer Specified in bottom byte of another register.
Barrel Shifter
Used for multiplication by constant
Immediate value
8 bit number, with a range of 0-255.
ALU
Rotated right through even number of positions
Allows increased range of 32-bit constants to be loaded directly into registers
Result
39v10 The ARM Architecture
TM
20
20
Loading 32 bit constants
To allow larger constants to be loaded, the assembler offers a pseudoinstruction: LDR rd, =const This will either: Produce a MOV or MVN instruction to generate the value (if possible). or
Generate a LDR instruction with a PC-relative address to read the constant from a literal pool (Constant data area embedded in the code). => =>
For example LDR r0,=0xFF LDR r0,=0x55555555
MOV r0,#0xFF LDR r0,[PC,#Imm12] DCD 0x55555555
This is the recommended way of loading constants into a register
39v10 The ARM Architecture
TM
21
21
Multiply
Syntax:
MUL{<cond>}{S} Rd, Rm, Rs MLA{<cond>}{S} Rd,Rm,Rs,Rn [U|S]MULL{<cond>}{S} RdLo, RdHi, Rm, Rs [U|S]MLAL{<cond>}{S} RdLo, RdHi, Rm, Rs
Rd = Rm * Rs Rd = (Rm * Rs) + Rn RdHi,RdLo := Rm*Rs RdHi,RdLo := (Rm*Rs)+RdHi,RdLo
Cycle time
Basic MUL instruction
2-5 cycles on ARM7TDMI 1-3 cycles on StrongARM/XScale 2 cycles on ARM9E/ARM102xE
+1 cycle for ARM9TDMI (over ARM7TDMI) +1 cycle for accumulate (not on 9E though result delay is one cycle longer) +1 cycle for long
Above are general rules - refer to the TRM for the core you are using for the exact details
TM
39v10 The ARM Architecture
22
22
Single register data transfer
LDR LDRB LDRH LDRSB LDRSH
STR STRB STRH
Word Byte Halfword Signed byte load Signed halfword load
Memory system must support all access sizes
Syntax:
LDR{<cond>}{<size>} Rd, <address> STR{<cond>}{<size>} Rd, <address>
e.g. LDREQB
39v10 The ARM Architecture
TM
23
23
Address accessed
Address accessed by LDR/STR is specified by a base register plus an offset For word and unsigned byte accesses, offset can be
An unsigned 12-bit immediate value (ie 0 - 4095 bytes).
LDR r0,[r1,#8]
A register, optionally shifted by an immediate value
LDR r0,[r1,r2] LDR r0,[r1,r2,LSL#2]
This can be either added or subtracted from the base register:
LDR r0,[r1,#-8] LDR r0,[r1,-r2] LDR r0,[r1,-r2,LSL#2]
For halfword and signed halfword / byte, offset can be:
An unsigned 8 bit immediate value (ie 0-255 bytes). A register (unshifted).
Choice of pre-indexed or post-indexed addressing
39v10 The ARM Architecture
TM
24
24
Pre or Post Indexed Addressing?
Pre-indexed: STR r0,[r1,#12]
Offset 12 r1
0x20c
r0 0x5 0x5
Source Register for STR
Base Register
0x200
0x200
Auto-update form: STR r0,[r1,#12]!
Post-indexed: STR r0,[r1],#12
Updated Base Register Original Base Register r1 0x20c r1 0x200
0x200
Offset 12
0x20c
r0 0x5 0x5
Source Register for STR
39v10 The ARM Architecture
TM
25
25
Thumb
Thumb is a 16-bit instruction set
Optimised for code density from C code (~65% of ARM code size) Improved performance from narrow memory Subset of the functionality of the ARM instruction set Switch between ARM and Thumb using BX instruction
ADDS r2,r2,#1
0
Core has additional execution state - Thumb
31
32-bit ARM Instruction
For most instructions generated by compiler:
Conditional execution is not used Source and destination registers identical Only Low registers used Constants are of limited size Inline barrel shifter not used
15
ADD r2,#1
16-bit Thumb Instruction
39v10 The ARM Architecture
TM
26
26
Example ARM-based System
16 bit RAM
32 bit RAM Interrupt Controller
nIRQ nFIQ
Peripherals
I/O
8 bit ROM
ARM Core
39v10 The ARM Architecture
TM
27
27